• SYSOSC: Internal high-frequency oscillator (4MHz or 32MHz with factory trim, 16MHz or 24MHz with user
trim)
• LFXT/LFCKIN : low-frequency external crystal oscillator or digital clock input (32KHz)
• HFXT/HFCKIN: high-frequency external crystal oscillator or digital clock input (4 to 48MHz)
• SYSPLL: system phase locked loop with 3 outputs (32 to 80MHz)
The following clocks are distributed by the clock module for use by the processor, bus, and peripherals:
• MCLK: Main system clock for PD1 peripherals, derived from SYSOSC, LFCLK, or HSCLK, active in RUN and
SLEEP modes
• CPUCLK: Clock for the processor (derived from MCLK), active in RUN mode
• ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modes
• MFCLK: 4MHz fixed mid-frequency clock for peripherals, available in RUN, SLEEP, and STOP modes
• MFPCLK: 4MHz fixed mid-frequency precision clock, available in RUN, SLEEP, and STOP modes
• LFCLK: 32kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and
STANDBY modes
• ADCCLK: ADC clock, available in RUN, SLEEP and STOP modes
• CLK_OUT: Used to output a clock externally, available in RUN, SLEEP, STOP, and STANDBY modes
• HFCLK: High frequency clock derived from HFXT or HFCLK_IN, available in RUN and SLEEP mode
• HSCLK: High speed clock derived from HFCLK or the SYSPLL, available in RUN and SLEEP mode
• CANCLK: CAN functional clock, derived from HFCLK or SYSPLL
For more details, see the CKM chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference
Manual.
8.5 DMA
The direct memory access (DMA) controller allows movement of data from one memory address to another
without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory
to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode,
without having to awaken to move data to or from a peripheral.
The DMA in these devices support the following key features:
• 7 independent DMA transfer channels
– 3 full-feature channel (DMA0, DMA1 and DMA2), supporting repeated transfer modes
– 4 basic channels (DMA3, DMA4, DMA5 and DMA6) supporting single transfer modes
• Configurable DMA channel priorities
• Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer
capability
• Transfer counter block size supports up to 64k transfers of any data type
• Configurable DMA transfer trigger selection
• Active channel interruption to service other channels
• Early interrupt generation for ping-pong buffer architecture
• Cascading channels upon completion of activity on another channel
• Stride mode to support data re-organization, such as 3-phase metering applications
Table 8-2 lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control
bits in the DMA memory mapped registers. Please note that if the DMA controller is to be configured for DMA
transfers which access the SRAM, the ECC protected SRAM address region must not be used by the DMA
or the CPU. In cases where the DMA must access SRAM, configure the DMA and CPU to use only the parity
checked SRAM address region or the unchecked SRAM address region
Table 8-2. DMA Trigger Mapping
Trigger 0:12 Source Trigger 13:24 Source
0 Software 13 SPI1 Publisher 1
1 Generic Subscriber 0 (FSUB_0) 14 SPI1 Publisher 2
2 Generic Subscriber 1 (FSUB_1) 15 UART3 Publisher 1
3 AES Publisher 1 16 UART3 Publisher 2
www.ti.com
MSPM0G3507, MSPM0G3506, MSPM0G3505
SLASEX6A – FEBRUARY 2023 – REVISED JUNE 2023
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: MSPM0G3507 MSPM0G3506 MSPM0G3505
To Next Page
Loading...
Need help?
General
