Texas Instruments MSPM0G3507 User Manual

4 Functional Block Diagram
Figure 4-1 shows the MSPM0G350x functional block diagram.
SPI0
SPI1
CPU SUB SYSTEM
Arm
Cortex-M0+
f
max
= 80 MHz
NVIC
MPU
SWD + MTB
IOPORT
AHB BUS (MCLK)
FLASH
Up to 128KB
SRAM
Up to 32KB
ROM
BCR, BSL
CPU-ONLY PD1 PERIPHERAL BUS (MCLK)
DMA
7-ch
PD1 PERIPHERAL BUS (MCLK)
AES
CRC
TRNG
UART3
GPIO
tIOBUSt
PD0 PERIPHERAL BUS (ULPCLK)
12b ADC0
12b ADC1
TIMG0
TIMG8
UART0
I2C0
I2C1
IOMUX
PMCU (SYSCTL)
GPAMP
FLASHCTL
ULPCLK
ULPCLK
PD1, CPU ACCESS ONLY
PD1, CPU/DMA ACCESS
PD1/PD0, CPU/DMA ACCESS
PD0, CPU/DMA ACCESS
LEGEND
EVENTRTC
WWDT0
WWDT1
CAN-FD
TIMA0
TIMA1
TIMG6
TIMG7
TIMG12
32-bit
UART1
UART2
VREF
PD0 PERIPHERAL BUS (ULPCLK)
OPA0
OPA1
COMP0
COMP1
COMP2
TEMP SENSOR
SYSOSC
SYSPLL
LFXT
HFXT
LFOSC
CKM
LDO
PMU
BOR
POR
VBOOST
12b DAC0
DEBUG
RTC_OUT
TX, RX,
CTS, RTS
TX, RX,
CTS, RTS
SDA, SCL
2-CH
IN+, IN-,
OUT
DAC_OUT
IN+, IN-,
OUT
IN+, IN-,
OUT
VREF+,
VREF-
A0_x
A1_x
2-CH
2-CH
2-CH
2-CH
FAULT
4-CH
FAULT
POCI, PICO,
SCK, CSx
TX, RX,
CTS, RTS
TX, RX
PAx, PBx
LFXIN, LFXOUT
HFXIN, HFXOUT
ROSC
CLK_OUT, FCC_IN
VDD, VSS
VCORE, NRST
Each COMPx includes an 8b
reference DAC; COMP0 and
COMP1 reference DACs connect
to OPA0 and OPA1, respectively
2-CH
QEI/HALL
MATHACL
SWCLK,
SWDIO
Figure 4-1. MSPM0G350x Functional Block Diagram
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MSPM0G3507, MSPM0G3506, MSPM0G3505
SLASEX6A – FEBRUARY 2023 – REVISED JUNE 2023
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Texas Instruments MSPM0G3507 Specifications

General

Brand	Texas Instruments
Model	MSPM0G3507
Category	Motherboard
Language	English