RM46L852
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SPNS185 –SEPTEMBER 2012
4.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an
imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to
handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU’s
program status register (CPSR).
4.9.4 Master/Slave Access Privileges
The table below lists the access permissions for each bus master on the device. A bus master is a module
that can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.
Table 4-22. Master / Slave Access Matrix
MASTERS ACCESS MODE SLAVES ON MAIN SCR
Flash Module Non-CPU CRC EMIF, Slave Peripheral
Bus2 Interface: Accesses to Interfaces Control
OTP, ECC, Bank Program Flash Registers, All
7 and CPU Data Peripheral
RAM Memories, And
All System
Module Control
Registers And
Memories
CPU READ User/Privilege Yes Yes Yes Yes Yes
CPU WRITE User/Privilege No Yes Yes Yes Yes
DMA User Yes Yes Yes Yes Yes
POM User Yes Yes Yes Yes Yes
DAP Privilege Yes Yes Yes Yes Yes
HTU1 Privilege No Yes Yes Yes Yes
HTU2 Privilege No Yes Yes Yes Yes
EMAC User No Yes No Yes No
OHCI User No Yes No Yes No
4.9.5 Special Notes on Accesses to Certain Slaves
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU
(master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned OFF.
4.9.6 Parameter Overlay Module (POM) Considerations
• The POM can map onto up to 8MB of the internal or external memory space. The starting address and
the size of the memory overlay are configurable via the POM control registers. Care must be taken to
ensure that the overlay is mapped on to available memory.
• ECC must be disabled by software via CP15 in case POM overlay is enabled; otherwise ECC errors
will be generated.
• POM overlay must not be enabled when the flash and internal RAM memories are swapped via the
MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
Copyright © 2012, Texas Instruments Incorporated System Information and Electrical Specifications 79
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