Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M35
M37
M40
M39
M38
LSB
MSB
M41
M42
M34
M36
116
TMS320F28069
,
TMS320F28068
,
TMS320F28067
,
TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698F –NOVEMBER 2010–REVISED MARCH 2016
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TMS320F28064 TMS320F28063 TMS320F28062
Detailed Description Copyright © 2010–2016, Texas Instruments Incorporated
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
Table 6-46. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
(1)
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
M39 t
su(DRV-CKXH)
Setup time, DR valid before CLKX high 30 8P – 10 ns
M40 t
h(CKXH-DRV)
Hold time, DR valid after CLKX high 1 8P – 10 ns
M41 t
su(FXL-CKXH)
Setup time, FSX low before CLKX high 16P + 10 ns
M42 t
c(CKX)
Cycle time, CLKX 2P
(2)
16P ns
(1) 2P = 1/CLKG
Table 6-47. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER
MASTER SLAVE
UNIT
MIN MAX MIN MAX
M34 t
h(CKXL-FXL)
Hold time, FSX low after CLKX low P ns
M35 t
d(FXL-CKXH)
Delay time, FSX low to CLKX high 2P
(1)
ns
M36 t
d(CKXL-DXV)
Delay time, CLKX low to DX valid –2 0 3P + 6 5P + 20 ns
M37 t
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX low
P + 6 7P + 6 ns
M38 t
d(FXL-DXV)
Delay time, FSX low to DX valid 6 4P + 6 ns
Figure 6-42. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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