M51
M50
M47
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M48
M49
M43
LSB
MSB
M52
M44
M45
117
TMS320F28069
,
TMS320F28068
,
TMS320F28067
,
TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698F –NOVEMBER 2010–REVISED MARCH 2016
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TMS320F28064 TMS320F28063 TMS320F28062
Detailed DescriptionCopyright © 2010–2016, Texas Instruments Incorporated
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
Table 6-48. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
(1)
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
M49 t
su(DRV-CKXH)
Setup time, DR valid before CLKX high 30 8P – 10 ns
M50 t
h(CKXH-DRV)
Hold time, DR valid after CLKX high 1 8P – 10 ns
M51 t
su(FXL-CKXL)
Setup time, FSX low before CLKX low 8P + 10 ns
M52 t
c(CKX)
Cycle time, CLKX 2P
(2)
16P ns
(1) 2P = 1/CLKG
Table 6-49. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER
MASTER SLAVE
UNIT
MIN MAX MIN MAX
M43 t
h(CKXH-FXL)
Hold time, FSX low after CLKX high 2P
(1)
ns
M44 t
d(FXL-CKXL)
Delay time, FSX low to CLKX low P ns
M45 t
d(CKXL-DXV)
Delay time, CLKX low to DX valid –2 0 3P + 6 5P + 20 ns
M47 t
dis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
6 6P + 6 ns
M48 t
d(FXL-DXV)
Delay time, FSX low to DX valid 6 4P + 6 ns
Figure 6-43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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