Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M54
M58
M56
M53
M55
M59
M57
LSB
MSB
M60
M61
118
TMS320F28069
,
TMS320F28068
,
TMS320F28067
,
TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698F –NOVEMBER 2010–REVISED MARCH 2016
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TMS320F28064 TMS320F28063 TMS320F28062
Detailed Description Copyright © 2010–2016, Texas Instruments Incorporated
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
Table 6-50. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
(1)
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
M58 t
su(DRV-CKXL)
Setup time, DR valid before CLKX low 30 8P – 10 ns
M59 t
h(CKXL-DRV)
Hold time, DR valid after CLKX low 1 8P – 10 ns
M60 t
su(FXL-CKXL)
Setup time, FSX low before CLKX low 16P + 10 ns
M61 t
c(CKX)
Cycle time, CLKX 2P
(2)
16P ns
(1) 2P = 1/CLKG
Table 6-51. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
(1)
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER
MASTER SLAVE
UNIT
MIN MAX MIN MAX
M53 t
h(CKXH-FXL)
Hold time, FSX low after CLKX high P ns
M54 t
d(FXL-CKXL)
Delay time, FSX low to CLKX low 2P
(1)
ns
M55 t
d(CKXH-DXV)
Delay time, CLKX high to DX valid –2 0 3P + 6 5P + 20 ns
M56 t
dis(CKXH-DXHZ)
Disable time, DX high impedance following last
data bit from CLKX high
P + 6 7P + 6 ns
M57 t
d(FXL-DXV)
Delay time, FSX low to DX valid 6 4P + 6 ns
Figure 6-44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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