Xilinx AC701 User Manual

28 www.xilinx.com AC701 Evaluation Board
UG952 (v1.3) April 7, 2015
Chapter 1: AC701 Evaluation Board Features
Clock Multiplexer U3 SY89544UMG drives Bank 213 MGTREFCLK0 pins AA13 (P) and
AB13 (N).
See Table 1-10 for clock MUX U3 connections.
The multiplexer U3 clock input channel select nets are SFP_MGT_CLK_SEL[1:0].
Net SFP_MGT_CLK_SEL1 is wired to FPGA U1 pin C24 and net SFP_MGT_CLK_SEL0 is
wired to FPGA U1 pin B26 on FPGA U1 Bank 16.
The U3 multiplexer circuit is shown in Figure 1-15.
GTP SMA REFCLK
(differential pair)
J25
SMA_MGT_REFCLK_P (net name). See U4 IN0: GTP Transceiver SMA Clock
Input, page 34.
J26
SMA_MGT_REFCLK_N (net name). See U4 IN0: GTP Transceiver SMA Clock
Input, page 34.
Table 1-9: MGT Clock Multiplexer U3 and U4 Clock Sources (Cont’d)
Clock Name Reference Description
Table 1-10: Multiplexer U3 SY89544UMG MGT Clock Inputs
Clock Source
Schematic Net Name
SY89544UMG U3
Schematic Net Name
(1)
FPGA U1 Bank 213
Device Ref Pin Input
SEL
[1:0](2)
Pin Output Pin Pin Name
ICS84402I U2
7 EPHYCLK_Q0_P
IN0 00
4
10(Q)
11(QB)
SFP_MGT_CLK0_P
SFP_MGT_CLK0_N
AA13
AB13
MGTREFCLK0P
MGTREFCLK0N
6 EPHYCLK_Q0_N 2
SI5324C-GM U24
29 SI5324_OUT0_C_N
IN1 01
32
28 SI5324_OUT0_C_P 30
FMC HPC J30
D4
FMC1_HPC_
GBTCLK0_M2C_P
IN2 10
27
D5
FMC1_HPC_
GBTCLK0_M2C_N
25
Not connected IN3 11
23
21
Notes:
1. U3 output clock nets SFP_MGT_CLK0_P/N implement a series 0.1μF capacitor
2. SEL[1:0] nets SFP_MGT_CLK_SEL1 FPGA U1 pin C24 and SFP_MGT_CLK_SEL0 FPGA U1 pin B26.
The I/O standard is LVCMOS25 (IOSTANDARD assumes a default V
ADJ
of 2.5V)
Send Feedback

Xilinx AC701 Specifications

General

Brand	Xilinx
Model	AC701
Category	Motherboard
Language	English