Xilinx AC701 - Page 87

AC701 Board XDC File Listing
AC701 Evaluation Board www.xilinx.com 87
UG952 (v1.3) April 7, 2015
set_property PACKAGE_PIN B1 [get_ports DDR3_DQS4_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_N]
set_property PACKAGE_PIN V3 [get_ports DDR3_DQS3_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_P]
set_property PACKAGE_PIN V2 [get_ports DDR3_DQS3_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_N]
set_property PACKAGE_PIN AD1 [get_ports DDR3_DQS2_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_P]
set_property PACKAGE_PIN AE1 [get_ports DDR3_DQS2_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_N]
set_property PACKAGE_PIN AD5 [get_ports DDR3_DQS1_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_P]
set_property PACKAGE_PIN AE5 [get_ports DDR3_DQS1_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_N]
set_property PACKAGE_PIN V8 [get_ports DDR3_DQS0_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_P]
set_property PACKAGE_PIN W8 [get_ports DDR3_DQS0_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_N]
#DDR3 DM
set_property PACKAGE_PIN H9 [get_ports DDR3_DM7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]
set_property PACKAGE_PIN G5 [get_ports DDR3_DM6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM6]
set_property PACKAGE_PIN F3 [get_ports DDR3_DM5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM5]
set_property PACKAGE_PIN G1 [get_ports DDR3_DM4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM4]
set_property PACKAGE_PIN U7 [get_ports DDR3_DM3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM3]
set_property PACKAGE_PIN AA3 [get_ports DDR3_DM2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM2]
set_property PACKAGE_PIN AC4 [get_ports DDR3_DM1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM1]
set_property PACKAGE_PIN AC6 [get_ports DDR3_DM0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM0]
#DDR3 DATA
set_property PACKAGE_PIN E6 [get_ports DDR3_D63]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]
set_property PACKAGE_PIN D6 [get_ports DDR3_D62]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D62]
set_property PACKAGE_PIN H8 [get_ports DDR3_D61]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D61]
set_property PACKAGE_PIN G8 [get_ports DDR3_D60]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D60]
set_property PACKAGE_PIN F8 [get_ports DDR3_D59]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D59]
set_property PACKAGE_PIN F7 [get_ports DDR3_D58]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D58]
set_property PACKAGE_PIN H6 [get_ports DDR3_D57]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D57]
set_property PACKAGE_PIN G6 [get_ports DDR3_D56]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D56]
set_property PACKAGE_PIN J6 [get_ports DDR3_D55]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D55]
set_property PACKAGE_PIN J5 [get_ports DDR3_D54]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D54]
set_property PACKAGE_PIN L8 [get_ports DDR3_D53]
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