Xilinx AC701 - Page 88

Appendix C: Master Constraints File Listing
88 www.xilinx.com AC701 Evaluation Board
UG952 (v1.3) April 7, 2015
set_property IOSTANDARD SSTL15 [get_ports DDR3_D53]
set_property PACKAGE_PIN K8 [get_ports DDR3_D52]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D52]
set_property PACKAGE_PIN K7 [get_ports DDR3_D51]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D51]
set_property PACKAGE_PIN K6 [get_ports DDR3_D50]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D50]
set_property PACKAGE_PIN G4 [get_ports DDR3_D49]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D49]
set_property PACKAGE_PIN F4 [get_ports DDR3_D48]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D48]
set_property PACKAGE_PIN E5 [get_ports DDR3_D47]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D47]
set_property PACKAGE_PIN D5 [get_ports DDR3_D46]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D46]
set_property PACKAGE_PIN D4 [get_ports DDR3_D45]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D45]
set_property PACKAGE_PIN C4 [get_ports DDR3_D44]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D44]
set_property PACKAGE_PIN B4 [get_ports DDR3_D43]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D43]
set_property PACKAGE_PIN A4 [get_ports DDR3_D42]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D42]
set_property PACKAGE_PIN D3 [get_ports DDR3_D41]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D41]
set_property PACKAGE_PIN C3 [get_ports DDR3_D40]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D40]
set_property PACKAGE_PIN C2 [get_ports DDR3_D39]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D39]
set_property PACKAGE_PIN A3 [get_ports DDR3_D38]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D38]
set_property PACKAGE_PIN A2 [get_ports DDR3_D37]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D37]
set_property PACKAGE_PIN F2 [get_ports DDR3_D36]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D36]
set_property PACKAGE_PIN E2 [get_ports DDR3_D35]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D35]
set_property PACKAGE_PIN E1 [get_ports DDR3_D34]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D34]
set_property PACKAGE_PIN D1 [get_ports DDR3_D33]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D33]
set_property PACKAGE_PIN G2 [get_ports DDR3_D32]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D32]
set_property PACKAGE_PIN V1 [get_ports DDR3_D31]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D31]
set_property PACKAGE_PIN W1 [get_ports DDR3_D30]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D30]
set_property PACKAGE_PIN W5 [get_ports DDR3_D29]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D29]
set_property PACKAGE_PIN W4 [get_ports DDR3_D28]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D28]
set_property PACKAGE_PIN V6 [get_ports DDR3_D27]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D27]
set_property PACKAGE_PIN W6 [get_ports DDR3_D26]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D26]
set_property PACKAGE_PIN W3 [get_ports DDR3_D25]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D25]
set_property PACKAGE_PIN Y3 [get_ports DDR3_D24]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D24]
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