Xilinx AC701 User Manual

Appendix C: Master Constraints File Listing
98 www.xilinx.com AC701 Evaluation Board
UG952 (v1.3) April 7, 2015
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D31]
set_property PACKAGE_PIN AB25 [get_ports HDMI_R_D30]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D30]
set_property PACKAGE_PIN AA25 [get_ports HDMI_R_D29]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D29]
set_property PACKAGE_PIN AA23 [get_ports HDMI_R_D28]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D28]
set_property PACKAGE_PIN V23 [get_ports HDMI_R_D23]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D23]
set_property PACKAGE_PIN Y20 [get_ports HDMI_R_D22]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D22]
set_property PACKAGE_PIN U24 [get_ports HDMI_R_D21]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D21]
set_property PACKAGE_PIN W20 [get_ports HDMI_R_D20]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D20]
set_property PACKAGE_PIN W23 [get_ports HDMI_R_D19]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D19]
set_property PACKAGE_PIN U20 [get_ports HDMI_R_D18]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D18]
set_property PACKAGE_PIN V24 [get_ports HDMI_R_D17]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D17]
set_property PACKAGE_PIN U25 [get_ports HDMI_R_D16]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D16]
set_property PACKAGE_PIN U26 [get_ports HDMI_R_D11]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D11]
set_property PACKAGE_PIN W24 [get_ports HDMI_R_D10]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D10]
set_property PACKAGE_PIN W25 [get_ports HDMI_R_D9]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D9]
set_property PACKAGE_PIN W26 [get_ports HDMI_R_D8]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D8]
set_property PACKAGE_PIN V26 [get_ports HDMI_R_D7]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D7]
set_property PACKAGE_PIN Y26 [get_ports HDMI_R_D6]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D6]
set_property PACKAGE_PIN Y25 [get_ports HDMI_R_D5]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D5]
set_property PACKAGE_PIN AA24 [get_ports HDMI_R_D4]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D4]
set_property PACKAGE_PIN AB26 [get_ports HDMI_R_DE]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_DE]
set_property PACKAGE_PIN AC26 [get_ports HDMI_R_VSYNC]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_VSYNC]
set_property PACKAGE_PIN AA22 [get_ports HDMI_R_HSYNC]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_HSYNC]
set_property PACKAGE_PIN V21 [get_ports HDMI_R_CLK]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_CLK]
set_property PACKAGE_PIN W21 [get_ports HDMI_INT]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_INT]
set_property PACKAGE_PIN Y21 [get_ports HDMI_R_SPDIF]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_SPDIF]
set_property PACKAGE_PIN T20 [get_ports HDMI_SPDIF_OUT_LS]
set_property IOSTANDARD LVCMOS18 [get_ports HDMI_SPDIF_OUT_LS]
#ETHERNET
set_property PACKAGE_PIN U22 [get_ports PHY_TX_CLK]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_TX_CLK]
set_property PACKAGE_PIN U21 [get_ports PHY_RX_CLK]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_RX_CLK]
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Xilinx AC701 Specifications

General

Brand	Xilinx
Model	AC701
Category	Motherboard
Language	English