Xilinx AC701 User Manual

AC701 Board XDC File Listing
AC701 Evaluation Board www.xilinx.com 99
UG952 (v1.3) April 7, 2015
set_property PACKAGE_PIN V18 [get_ports PHY_RESET_B]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_RESET_B]
set_property PACKAGE_PIN W18 [get_ports PHY_MDC]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDC]
set_property PACKAGE_PIN T14 [get_ports PHY_MDIO]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDIO]
set_property PACKAGE_PIN T15 [get_ports PHY_TX_CTRL]
set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TX_CTRL]
set_property PACKAGE_PIN U14 [get_ports PHY_RX_CTRL]
set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RX_CTRL]
set_property PACKAGE_PIN U16 [get_ports PHY_TXD0]
set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD0]
set_property PACKAGE_PIN U15 [get_ports PHY_TXD1]
set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD1]
set_property PACKAGE_PIN T18 [get_ports PHY_TXD2]
set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD2]
set_property PACKAGE_PIN T17 [get_ports PHY_TXD3]
set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD3]
set_property PACKAGE_PIN U17 [get_ports PHY_RXD0]
set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD0]
set_property PACKAGE_PIN V17 [get_ports PHY_RXD1]
set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD1]
set_property PACKAGE_PIN V16 [get_ports PHY_RXD2]
set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD2]
set_property PACKAGE_PIN V14 [get_ports PHY_RXD3]
set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD3]
#SDIO
set_property PACKAGE_PIN P19 [get_ports SDIO_DAT0]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT0]
set_property PACKAGE_PIN N19 [get_ports SDIO_DAT1]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT1]
set_property PACKAGE_PIN P23 [get_ports SDIO_DAT2]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT2]
set_property PACKAGE_PIN P21 [get_ports SDIO_CD_DAT3]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CD_DAT3]
set_property PACKAGE_PIN N23 [get_ports SDIO_CMD]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CMD]
set_property PACKAGE_PIN N24 [get_ports SDIO_CLK]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CLK]
set_property PACKAGE_PIN P24 [get_ports SDIO_SDDET]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_SDDET]
set_property PACKAGE_PIN R20 [get_ports SDIO_SDWP]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_SDWP]
#FMC VADJ ON-OFF
set_property PACKAGE_PIN R16 [get_ports FMC_VADJ_ON_B]
set_property IOSTANDARD LVCMOS33 [get_ports FMC_VADJ_ON_B]
#PWRGOOD
set_property PACKAGE_PIN P15 [get_ports CTRL2_PWRGOOD]
set_property IOSTANDARD LVCMOS33 [get_ports CTRL2_PWRGOOD]
#SFP MGT CLK
set_property PACKAGE_PIN AB13 [get_ports SFP_MGT_CLK0_N]
set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_N]
set_property PACKAGE_PIN AA13 [get_ports SFP_MGT_CLK0_P]
set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_P]
set_property PACKAGE_PIN AA11 [get_ports SFP_MGT_CLK1_P]
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Xilinx AC701 Specifications

General

Brand	Xilinx
Model	AC701
Category	Motherboard
Language	English