128 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
www.xilinx.com UG257 (v1.1) December 5, 2007
Chapter 16: XC2C64A CoolRunner-II CPLD
R
UCF Location Constraints
There are two sets of constraints listed below–one for the Spartan-3E FPGA and one for the
XC2C64A CoolRunner-II CPLD.
Figure 16-1: XC2C64A CoolRunner-II CPLD Controls Master Serial and BPI Configuration Modes
(N18)
Spartan-3E FPGA
(P29)
(P18)
XC_CMD<1>
XC_CMD<0>
XC2C64A VQ44
CoolRunner-II CPLD
(P30)
XC_D<2>
XC_D<1>
XC_D<0>
(P36)
(P34)
(P33)
(P8)
(P6)
(F17)
(F18)
(G16)
(T10)
(V11)
FPGA_M2
FPGA_M1
(P5)
(M10)
FPGA_M0
XC_CPLD_EN
XC_TRIG
(P42)
(P41)
(D10)
(R17)
XC_DONE
(P40)
DONE
XC_PROG_B
(P39)
PROG_B
XC_GCK0
(P43)
GCLK10
(H16)
(C9)
(P1)
SPI_SCK
(P44)
(U16)
(P23)
(P22)
(P21)
(P20)
(P19)
(FX2_IO<32>)
SF_A<23>
SF_A<22>
SF_A<21>
SF_A<20>
3.3V
(P16)
XC_WDT_EN
(A11)
(N11)
(V12)
(V13)
(T12)
(P2)
XC_PF_CE
XCF04S
Platform Flash PROM
CE
Intel StrataFlash
JP10
WDT_EN
A[19:0] A[19:0]
A[24:20]
During Configuration:
BPI Up: A[24:20]=00000
BPI Down: A[24:20]=11111
After Configuration or Other Modes:
A[24:20]=ZZZZ
Required for Master Serial Mode
Enable Platform Flash PROM when
M[2:0]=000
A[23:20]
A[23:20] Unconnected
SF_A<19:0>
SF_A<24>
Upper Address
Control During
Configuration
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