108 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 3: Analog Design Considerations
R
Deterministic Jitter (DJ) is data pattern dependant jitter, attributed to a unique source (e.g.,
Inter Symbol Interference (ISI) due to loss effects of the media). DJ is linearly additive.
Random Jitter (RJ) is due to stochastic sources, such as substrate, power supply, etc. RJ is
additive as the sum of squares, and follows a bell curve.
Clock and Data Recovery
The serial transceiver input is locked to the input data stream through Clock and Data
Recovery (CDR), a built-in feature of the RocketIO transceiver. CDR keys off the rising and
falling edges of incoming data and derives a clock that is representative of the incoming
data rate.
The derived clock, RXRECCLK, is presented to the FPGA fabric at 1/20th the incoming
data rate (whether full-rate or half-rate). This clock is generated and remains locked as
long as it remains within the specified component range. This range is shown in Table 3-4.
A sufficient number of transitions must be present in the data stream for CDR to work
properly. The CDR circuit is guaranteed to work with 8B/10B encoding. Further, CDR
requires approximately 5,000 transitions upon power-up to guarantee locking to the
incoming data rate. Once lock is achieved, up to 75 missing transitions can be tolerated
before lock to the incoming data stream is lost.
Table 3-4: CDR Parameters
Parameter Min Typ Max Units Conditions
Frequency Range Serial input, diff.
(RXP/RXN)
300 1,562.5 MHz
TDCREF REFCLK
(1)
duty cycle 45 50 55 %
TRCLK/TFCLK REFCLK
(1)
rise and
fall time (see
Virtex-II Pro Data
Sheet, Module 3)
600 1000 ps Between 20%
and 80% voltage
levels
TGJTT REFCLK
(1)
total
jitter,
(2)
peak-to-peak
40 ps 3.125 Gb/s
50 ps 2.5 Gb/s
120 ps 1.06 Gb/s
TLOCK
(3)
Clock recovery
frequency acquisition
time
10 µs From system
reset. Much less
time is needed to
lock if loss of
sync occurs
(T
phase
), which is
described in Data
Sheet Module 3.
TUNLOCK cycles
PLL length 75 non-
transitions
Requirement
when bypassing
8B/10B
Notes:
1. BREFCLK for speeds of 2.5 Gb/s or greater.
2. Jitter measured at BGA ball.
3. T
LOCK
depends on serial speed and length/type of sequence used.
Product Not Recommended for New Designs
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