Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com 43
UG024 (v3.0) February 22, 2007
Clocking
R
Example 1a: Two-Byte Clock with DCM
The following HDL codes are examples of a simple clock scheme using 2-byte data with
both USRCLK and USRCLK2 at the same frequency. USRCLK_M is the input for both
USRCLK and USRCLK2.
VHDL Template
-- Module: TWO_BYTE_CLK
-- Description: VHDL submodule
-- DCM for 2-byte GT
--
-- Device: Virtex-II Pro Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity TWO_BYTE_CLK is
port (
REFCLKIN : in std_logic;
Table 2-5: DCM Outputs for Different DATA_WIDTHs
SERDES_10B
TX_DATA_WIDTH
RX_DATA_WIDTH
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
FALSE 1 CLKIN CLK0 CLK2X180
FALSE 2 CLKIN CLK0 CLK0
FALSE 4 CLKIN CLK180
(1)
CLKDV (divide by 2)
TRUE 1 CLKIN CLKDV (divide by 2) CLK180
(1)
TRUE 2 CLKIN CLKDV (divide by 2) CLKDV (divide by 2)
TRUE 4 CLKIN CLKFX180 (divide by 2) CLKDV (divide by 4)
Notes:
1. Since CLK0 is needed for feedback, it can be used instead of CLK180 to clock USRCLK or USRCLK2 of the transceiver with the use
of the transceiver’s local inverter, saving a global buffer (BUFG).
Figure 2-2: Two-Byte Clock with DCM
MGT + DCM for 2-Byte Data Path
GT_std_2
REFCLKSEL
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
CLKIN
CLKFB
RST
DCM
CLK0
0
REFCLK_P
BUFG
IBUFGDS
Clocks for 2-Byte Data Path
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
REFCLK
REFCLK_N
ug024_02a_112202
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English