Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com 89
UG024 (v3.0) February 22, 2007
Fabric Interface (Buffers)
R
TXFORCECRCERR,
TX_CRC_FORCE_VALUE
To test the CRC logic in either the MGT or the FPGA fabric, TXFORCECRCERR and
TX_CRC_FORCE_VALUE may be used to invoke a CRC error. When TXFORCECRCERR
is asserted High for at least one USRCLK2 cycle during data transmission (between SOP
and EOP), the CRC circuitry is forced to XOR TXDATA with TX_CRC_FORCE_VALUE,
creating a bit error. This should cause the receiver to register that a CRC error has occurred.
RocketIO CRC Support Limitations
There are limitations to the CRC support provided by the RocketIO transceiver core:
• RocketIO CRC support is implementable for single-channel use only. Computation
and byte-striping of CRC across multiple bonded channels is not supported. For that
usage, the CRC logic can be implemented in the FPGA fabric.
• The RocketIO transceiver does not compute the 16-bit variant CRC used for
Infiniband, and thus does not fulfill the Infiniband CRC requirement. Infiniband CRC
can be computed in the FPGA fabric.
• All CRC formats have minimum allowable packet sizes. These limits are larger than
those set by the user mode, and are defined by the specific protocol.
Fabric Interface (Buffers)
Overview: Transmitter and Elastic (Receiver) Buffers
Both the transmitter and the receiver include buffers (FIFOs) in the data path. This section
gives the reasons for including the buffers and outlines their operation.
Transmitter Buffer (FIFO)
The transmitter buffer’s write pointer (TXUSRCLK) is frequency-locked to its read pointer
(REFCLK). Therefore, clock correction and channel bonding are not required. The purpose
of the transmitter's buffer is to accommodate a phase difference between TXUSRCLK and
REFCLK. Proper operation of the circuit is only possible if the FPGA clock (TXUSRCLK) is
frequency-locked to the reference clock (REFCLK). Phase variations of up to one clock
cycle are allowable. A simple FIFO suffices for this purpose. A FIFO depth of four permits
reliable operation with simple detection of overflow or underflow, which might occur if
the clocks are not frequency-locked. Overflow or underflow conditions are detected and
signaled at the interface.
Receiver Buffer
The receiver buffer is required for two reasons:
• To accommodate the slight difference in frequency between the recovered clock
RXRECCLK and the internal FPGA core clock RXUSRCLK (clock correction)
• To allow realignment of the input stream to ensure proper alignment of data being
read through multiple transceivers (channel bonding)
The receiver uses an elastic buffer, where “elastic” refers to the ability to modify the read
pointer for clock correction and channel bonding.
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English