Xilinx RocketIO User Manual

56 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 2: Digital Design Considerations
R
RXRECCLK
RXRECCLK is a recovered clock derived by dividing by 20 the received data stream bit rate
(whether full-rate or half-rate). If clock correction is bypassed, it is not possible to
compensate for differences in the clock embedded in the received data and the REFCLK-
created USRCLKs. In this case, RXRECCLK is used to generate the RXUSRCLKs, as shown
in Figure 2-11.
RXRECCLK changes monotonically when it changes from being locked to the reference
clock to being locked to data and vice versa. The recovered bit clock jumps by a maximum
of 1/16th of a bit period every eight RXRECCLK cycles (20 ps for a data rate of 3.125 Gb/s
with a 320-ps bit period) in the interpolator. RXRECCLK is derived from this bit clock
through a divide-by-20 process. When the data input is kept static, however, the recovered
clock does not frequency-lock to the reference clock exactly, but can deviate from it by up
to 400 ppm.
Note:
Bypassing the RX elastic buffer is not recommended, as the skew created by the DCM
and routing to global clock resources is uncertain and may cause unreliable performance.
Clock Dependency
All signals used by the FPGA fabric to interact between user logic and the transceiver
depend on an edge of USRCLK2. These signals all have setup and hold times with respect
to this clock. For specific timing values, see Module 3 of the Virtex-II Pro data sheet. The
timing relationships are further discussed and illustrated in Appendix A, “RocketIO
Transceiver Timing Model.”
Figure 2-11: Using RXRECCLK to Generate RXUSRCLK and RXUSRCLK2
REFCLKSEL
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
RXRECCLK
CLKIN
CLKFB
RST
DCM
CLK0
0
BUFG
UG024_38_112202
REFCLK_P
IBUFGDS
REFCLK_N
BUFG
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English