Xilinx RocketIO User Manual

24 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 1: RocketIO Transceiver Overview
R
List of Available Ports
The RocketIO transceiver primitives contain 50 ports, with the exception of the 46-port
GT_ETHERNET and GT_FIBRE_CHAN primitives. The differential serial data ports
(RXN, RXP, TXN, and TXP) are connected directly to external pads; the remaining 46 ports
are all accessible from the FPGA logic (42 ports for GT_ETHERNET and
GT_FIBRE_CHAN).
Table 1-5 contains the port descriptions of all primitives.
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports
Port I/O
Port
Size
Definition
BREFCLK I 1 This high-quality reference clock uses dedicated routing to improve
jitter for serial speeds of 2.5 Gb/s or greater. See Table 2-2, page 40 for
usage cases.
BREFCLK2 I 1 Alternative to BREFCLK. Can be selected by REFCLKSEL.
CHBONDDONE
(2)
O 1 Indicates a receiver has successfully completed channel bonding when
asserted High.
CHBONDI
(2)
I 4 The channel bonding control that is used only by “slaves” which is
driven by a transceiver's CHBONDO port.
CHBONDO
(2)
O 4 Channel bonding control that passes channel bonding and clock
correction control to other transceivers.
CONFIGENABLE I 1 Reconfiguration enable input (unused). Should be set to logic 0.
CONFIGIN I 1 Data input for reconfiguring transceiver (unused). Should be set to
logic 0.
CONFIGOUT O 1 Data output for configuration readback (unused). Should be left
unconnected.
ENCHANSYNC
(2)
I 1 Comes from the core to the transceiver and enables the transceiver to
perform channel bonding
ENMCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on minus-comma.
High realigns serial bitstream byte boundary when minus-comma is
detected.
ENPCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on plus-comma. High
realigns serial bitstream byte boundary when plus-comma is detected.
LOOPBACK I 2 Selects the two loopback test modes. Bit 1 is for serial loopback and bit 0
is for internal parallel loopback.
POWERDOWN I 1 Shuts down both the receiver and transmitter sides of the transceiver
when asserted High. This decreases the power consumption while the
transceiver is shut down. This input is asynchronous.
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English