120 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 3: Analog Design Considerations
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Other Important Design Notes
Powering the RocketIO Transceivers
IMPORTANT! All RocketIO transceivers in the FPGA, whether instantiated in the design
or not, must be connected to power and ground. Unused transceivers may be powered by
any 2.5 V source, and passive filtering is not required.
The maximum power consumption per port is 350 mW at 3.125 Gb/s operation.
Pin Connections on the Unused RocketIO Transceivers
When the Entire MGT Is Unused
• The TXP/TXN and RXP/RXN pins must be left unconnected.
• The AVCCAUXRX and AVCCAUXTX pins must be connected to a 2.5V supply, but
that supply does not need a linear regulator or filter network.
• The VTTX and VTRX pins must be connected to a 2.5V supply, but that supply does
not need a linear regulator or filter network.
• GNDA must be connected to ground.
When Only Part of the MGT Is Used
This could occur, for example, if the MGT is used as a TX or an RX, but not both.
• Both AVCCAUXRX and AVCCAUXTX must be connected to power with passive
filtering.
• GNDA must be connected to ground.
• Both VTTX and VTRX must be connected to power with passive filtering.
The unused TX or RX pins can be unconnected. If the MGT is used as a receiver, the TX pins
can be left unconnected. If the design uses the transmitter, the RX pins can safely be left
unconnected, and oscillations will not cause erroneous behavior because the termination
resistors (50Ω or 75Ω) act as pull-ups on the line.
The POWERDOWN Port
POWERDOWN is a single-bit primitive port (see Table 2-5, page 43) that allows shutting
off the transceiver in case it is not needed for the design, or will not be transmitting or
receiving for a long period of time. When POWERDOWN is asserted, the transceiver does
not use any power. The clocks are disabled and do not propagate through the core. The
3-state TXP and TXN pins are set High-Z, while the outputs to the fabric are frozen but not
set High-Z.
Any given transceiver that is not instantiated in the design will automatically be set to the
POWERDOWN state by the Xilinx ISE development software, and will consume no power.
An instantiated transceiver, however, will consume some power, even if it is not engaged
in transmitting or receiving. Therefore, when a transceiver is not to be used for an extended
period of time, the POWERDOWN port should be asserted High to reduce overall power
consumption by the Virtex-II Pro FPGA.
Deasserting the POWERDOWN port restores the transceiver to normal functional status.
When POWERDOWN is toggled, the PMA is properly initialized.
Product Not Recommended for New Designs