Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com 85
UG024 (v3.0) February 22, 2007
CRC (Cyclic Redundancy Check)
R
CRC Latency
Enabling CRC increases the transmission latency from TXDATA to TXP and TXN. The
enabling of CRC does not affect the latency from RXP and RXN to RXDATA. The typical
and maximum latencies, expressed in TXUSRCLK/RXUSRCLK cycles, are shown in
Table 2-20. For timing diagrams expressing these relationships, please see Module 3 of the
Virtex-II Pro Data Sheet
.
Ports and Attributes
TX_CRC_USE,
RX_CRC_USE
These two attributes control whether the MGT CRC circuitry is enabled or bypassed. When
set to TRUE, CRC is enabled. When set to FALSE, CRC is bypassed and must be
implemented in the FPGA fabric.
CRC_FORMAT
There are four possible CRC modes: USER_MODE, FIBRE_CHAN, ETHERNET, and
INFINIBAND. This attribute is modifiable only for the GT_XAUI and GT_CUSTOM
primitives. Each mode has a Start of Packet (SOP) and End of Packet (EOP) setting to
determine where to start and end the CRC monitoring. USER_MODE allows the user to
define the SOP and EOP by setting the CRC_START_OF_PKT and CRC_END_OF_PKT to
one of the valid K-characters (Table B-2, page 143). The CRC is controlled by RX_CRC_USE
and TX_CRC_USE. Whenever these attributes are set to TRUE, CRC is used.
The four modes are defined in the subsections following.
USER_MODE
USER_MODE is the simplest CRC methodology. The CRC checks for the SOP and EOP,
calculates CRC on the data, and leaves the four remainders directly before the EOP. The
CRC form for the user-defined mode is shown in Figure 2-24, along with the timing for
when RXCHECKINGCRC and RXCRCERR are asserted High with respect to the incoming
data.
To check the CRC error detection logic in a testing mode such as serial loopback, a CRC
error can be forced by setting TXFORCECRCERR to High, which incorporates an error into
the transmitted data. When that data is received, it appears “corrupted,” and the receiver
Table 2-20: Effects of CRC on Transceiver Latency
(1)
TXDATA to TXP and TXN
in TXUSRCLK Cycles
RXP and RXN to RXDATA
in RXUSRCLK Cycles
(3)
Typical Maximum Typical Maximum
CRC Disabled 8 11 25 42
(2)
CRC Enabled 14 17 25 42
(2)
Notes:
1. See Table 2-6 and Table 2-7 for all MGT block latency parameters.
2. This maximum may occur when certain conditions are present, and clock correction and channel
bonding are enabled. If these functions are both disabled, the maximum will be near the typical
values.
3. To further reduce receive-side latency, refer to Appendix C, “Related Online Documents.”
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English