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Xilinx RocketIO User Manual

Xilinx RocketIO
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74 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 2: Digital Design Considerations
R
Clock correction may be used with other encoding protocols, but they must have a 10-bit
alignment scheme. This is required so the comma detection logic can properly align the
data in the elastic buffer, allowing the clock correction logic to properly read out data to the
FPGA fabric.
RX_BUFFER_USE
The RX_BUFFER_USE attribute controls if the elastic buffer is bypassed or not. Most
applications use this buffer for clock correction and channel bonding. (See “Channel
Bonding (Channel Alignment),” page 79.) It is recommended that this attribute always be
set to TRUE, since this buffer allows a way to cross the clock domains of RXRECCLK and
the fabric RXUSRCLK/RXUSRCLK2.
CLK_COR_SEQ_*_*
To accommodate many different protocols, the MGT features programmability that allows
it to detect a 1-, 2-, or 4-byte clock correction sequence (CCS), such as may be used in
Gigabit Ethernet (2-byte) or Fibre Channel (4-byte). The attributes CLK_COR_SEQ_*_*
and CLK_COR_SEQ_LEN (below) define the CCS that the PCS recognizes. Both SEQ_1
and SEQ_2 can be used at the same time if multiple CCSs are required. As shown in
Table 2-15, the example CCS has two possible modes, one for when 8B/10B encoding is
used, the other for when 8B/10B encoding is bypassed. The most significant bit of the CCS
determines whether it is applicable to an 8-bit (encoded) or a 10-bit (unencoded) sequence.
These sequences require that the encoding scheme allows the comma detection and
alignment circuitry to properly align data in the elastic buffer. (See
“CLK_CORRECT_USE”, above). The bit definitions are the same as shown earlier in the
Vitesse channel-bonding example. (See “Receiving Vitesse Channel Bonding Sequence.”)
Table 2-15: Clock Correction Sequence / Data Correlation for 16-Bit Data Port
Attribute Settings
Character CHARISK
TXDATA
(hex)
CLK_COR_SEQ 8-Bit Data Mode
10-Bit Data Mode
(8B/10B Bypass)
CLK_COR_SEQ_1_1
00110111100 10011111010 K28.5 1
BC
CLK_COR_SEQ_1_2 00010010101 11010100010 D21.4 0 95
CLK_COR_SEQ_1_3 00010110101 11010101010 D21.5 0 Β5
CLK_COR_SEQ_1_4 00010110101 11010101010 D21.5 0 Β5
Product Not Recommended for New Designs

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Xilinx RocketIO Specifications

General IconGeneral
BrandXilinx
ModelRocketIO
CategoryTransceiver
LanguageEnglish

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