Xilinx RocketIO - Page 59

RocketIO™ Transceiver User Guide www.xilinx.com 59
UG024 (v3.0) February 22, 2007
Reset/Power Down
R
process (USRCLK2_M, DCM_LOCKED)
begin
if (USRCLK2_M' event and USRCLK2_M = '1') then
if(DCM_LOCKED = '0') then
startup_count <= "00000000";
elsif (DCM_LOCKED = '1') then
startup_count <= startup_count + "00000001";
end if;
end if;
if (USRCLK2_M' event and USRCLK2_M = '1') then
if(DCM_LOCKED = '0') then
RST <= '1';
elsif (startup_count = "00000010") then
RST <= '0';
end if;
end if;
end process;
end RTL;
Verilog Template
// Module: gt_reset
// Description: Verilog Submodule
// reset for4-byte GT
//
// Device: Virtex-II Pro Family
module gt_reset(
USRCLK2_M,
DCM_LOCKED,
RST
);
input USRCLK2_M;
input DCM_LOCKED;
output RST;
wire USRCLK2_M;
wire DCM_LOCKED;
reg RST;
reg [7:0] startup_counter;
always @ ( posedge USRCLK2_M )
if ( !DCM_LOCKED )
startup_counter <= 8'h0;
else if ( startup_counter != 8'h02 )
startup_counter <= startup_counter + 1;
always @ ( posedge USRCLK2_M or negedge DCM_LOCKED )
if ( !DCM_LOCKED )
RST <= 1'b1;
else
RST <= ( startup_counter != 8'h02 );
endmodule
Product Not Recommended for New Designs