Xilinx VCU128 User Manual

For more informaon on the internal VREF, see the "Supply Voltages for the SelectIO Pins",
“VREF”, and “Internal VREF” secons in the UltraScale Architecture SelectIO Resources User Guide
(UG571). For more details about the Micron RLD3 component memory, see the Micron
MT44K32M36RB Data Sheet at the Micron Technology website.
QDR4 Component Memory
[Figure 2, callout 6]
The 4.5 GB QDR4 component memory system is comprised of one 144-Mbit density (4M × 36)
QDR4 SRAM device located at U40.
•
Manufacturer: Cypress
•
Part Number: CY7C4142KV13_106FCXC
•
Descripon:
○ 144-Mbit density (4M × 36)
○ Dual independent 36-bit bidireconal double data rate (DDR) data ports
○ Supports concurrent read/write transacons on both ports
○ Single address port used to control both data ports
○ 1.2V 361-ball FCBGA
○ Maximum operang frequency of 1066 MHz
The VCU128 XCVU37P FPGA QDR IV interface performance is documented in the Virtex
UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
The 72-bit wide QDR4 memory is connected to XCVU37P U1 HP banks 68, 69, and 70. The
QDR4 memory interface bank VREF pins are not connected, which, coupled with an XDC
set_property INTERNAL VREF constraint, invoke the INTERNAL VREF mode. The connecons
between the 72-bit interface QDR4 component memories and XCVU37P banks 68, 69, and 70
are listed in the following table.
Chapter 3: Board Component Descriptions
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 29
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Xilinx VCU128 Specifications

General

Brand	Xilinx
Model	VCU128
Category	Motherboard
Language	English