Xilinx VCU128 - Page 56

Table 15: XCVU37P U1 GTY Transceiver Bank 131 Connections
MGT
Bank
FPGA
(U1)
Pin
FPGA (U1) Pin
Name
Schematic Net
Name
Connected
Pin
Connected
Pin Name
Connected
Device
GTY bank
131
AA44 MGTYTXP0_131 QSFP4_TX1_P 36 TX1P
QSFP2 J32
AA45
MGTYTXN0_131 QSFP4_TX1_N 37 TX1N
AA53 MGTYRXP0_131 QSFP4_RX1_P 17 RX1P
AA54 MGTYRXN0_131 QSFP4_RX1_N 18 RX1N
Y46 MGTYTXP1_131 QSFP4_TX2_P 3 TX2P
Y47 MGTYTXN1_131 QSFP4_TX2_N 2 TX2N
Y51 MGTYRXP1_131 QSFP4_RX2_P 22 RX2P
Y52 MGTYRXN1_131 QSFP4_RX2_N 21 RX2N
W48 MGTYTXP2_131 QSFP4_TX3_P 33 TX3P
W49 MGTYTXN2_131 QSFP4_TX3_N 34 TX3N
W53 MGTYRXP2_131 QSFP4_RX3_P 14 RX3P
W54 MGTYRXN2_131 QSFP4_RX3_N 15 RX3N
W44 MGTYTXP3_131 QSFP4_TX4_P 6 TX4P
W45 MGTYTXN3_131 QSFP4_TX4_N 5 TX4N
V51 MGTYRXP3_131 QSFP4_RX4_P 25 RX4P
V52 MGTYRXN3_131 QSFP4_RX4_N 24 RX4N
AB42 MGTREFCLK0P_131 QSFP4_SI570_CLOCK_P
1
4 OUT
U80 SI570 I2C
prog. osc.
AB43 MGTREFCLK0N_131 QSFP4_SI570_CLOCK_N
1
5 OUT_B
AA40 MGTREFCLK1P_131 SMA_REFCLK_INPUT_P
1
1 SIG
SMA J24 (P)
SMA J26 (N)
AA41 MGTREFCLK1N_131 SMA_REFCLK_INPUT_N
1
1 SIG
Notes:
1. Series 0.01uF capacitor coupled.
Chapter 3: Board Component Descriptions
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 56
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