Xilinx VCU128 User Manual

○ Four GTY transceivers allocated to PCIe lanes 7:4 PCIE_EP_TX/RX[7:4]
• Quad 225
○ MGTREFCLK0 - PCIE_CLK1_P/N (U94)
○ MGTREFCLK1 - not connected
○ Four GTY transceivers allocated to PCIe lanes 11:8 PCIE_EP_TX/RX[11:8]
• Quad 224
○ MGTREFCLK0 - not connected
○ MGTREFCLK1 - not connected
○ Four GTY transceivers allocated to PCIe lanes 15:12 PCIE_EP_TX/RX[15:12]
The XCVU37P le-side GTY transceiver interface assignments are shown in the following gure.
Figure 21: XCVU37P Left-side GTY Transceiver Assignments
BANK 227
MGTY_227_0
MGTY_227_1
MGTY_227_2
MGTY_227_3
MGTY_227_REFCLK0
MGTY_227_REFCLK1
PCIE_EP_TX/RX_3
PCIE_EP_TX/RX_2
PCIE_EP_TX/RX_1
PCIE_EP_TX/RX_0
PCIE_CLK2
NC
BANK 225
MGTY_225_0
MGTY_225_1
MGTY_225_2
MGTY_225_3
MGTY_225_REFCLK0
MGTY_225_REFCLK1
PCIE_EP_TX/RX_11
PCIE_EP_TX/RX_10
PCIE_EP_TX/RX_9
PCIE_EP_TX/RX_8
PCIE_CLK1
NC
BANK 226
MGTY_226_0
MGTY_226_1
MGTY_226_2
MGTY_226_3
MGTY_226_REFCLK0
MGTY_226_REFCLK1
PCIE_EP_TX/RX_7
PCIE_EP_TX/RX_6
PCIE_EP_TX/RX_5
PCIE_EP_TX/RX_4
NC
NC
BANK 224
MGTY_224_0
MGTY_224_1
MGTY_224_2
MGTY_224_3
MGTY_224_REFCLK0
MGTY_224_REFCLK1
PCIE_EP_TX/RX_15
PCIE_EP_TX/RX_14
PCIE_EP_TX/RX_13
PCIE_EP_TX/RX_12
NC
NC
X21651-092618
Left-side GTY Transceiver Connectivity
The following tables list the XCVU37P FPGA U1 GTY transceiver banks 227, 226, 225, and 224
connecons, respecvely.
For addional informaon on GTY transceivers, see the UltraScale Architecture GTY Transceivers
User Guide (UG578). Also see the UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide
(PG182). For addional informaon about the quad small form factor pluggable (28 Gb/s
QSFP28) module, see the SFF-8663 and SFF-8679 specicaons for the 28 Gb/s QSFP+ at the
SNIA Technology Aliates website.
Chapter 3: Board Component Descriptions
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 63
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Xilinx VCU128 Specifications

General

Brand	Xilinx
Model	VCU128
Category	Motherboard
Language	English