Xilinx VCU128 - Page 62

Table 21: XCVU37P U1 GTY Transceiver Bank 124 Connections
MGT
Bank
FPGA
(U1)
Pin
FPGA (U1) Pin
Name
Schematic Net Name
Connected
Pin
Connected
Pin Name
Connected
Device
GTY
Bank
124
BC48 MGTYTXP0_124 FMCP_HSPC_DP0_C2M_P C2 DP0_C2M_P
FMCP HSPC
J18
BC49 MGTYTXN0_124 FMCP_HSPC_DP0_C2M_N C3 DP0_C2M_N
BC53 MGTYRXP0_124 FMCP_HSPC_DP0_M2C_P C6 DP0_M2C_P
BC54 MGTYRXN0_124 FMCP_HSPC_DP0_M2C_N C7 DP0_M2C_N
BC44 MGTYTXP1_124 FMCP_HSPC_DP1_C2M_P A22 DP1_C2M_P
BC45 MGTYTXN1_124 FMCP_HSPC_DP1_C2M_N A23 DP1_C2M_N
BB51 MGTYRXP1_124 FMCP_HSPC_DP1_M2C_P A2 DP1_M2C_P
BB52 MGTYRXN1_124 FMCP_HSPC_DP1_M2C_N A3 DP1_M2C_N
BB46 MGTYTXP2_124 FMCP_HSPC_DP2_C2M_P A26 DP2_C2M_P
BB47 MGTYTXN2_124 FMCP_HSPC_DP2_C2M_N A27 DP2_C2M_N
BA53 MGTYRXP2_124 FMCP_HSPC_DP2_M2C_P A6 DP2_M2C_P
BA54 MGTYRXN2_124 FMCP_HSPC_DP2_M2C_N A7 DP2_M2C_N
BA44 MGTYTXP3_124 FMCP_HSPC_DP3_C2M_P A30 DP3_C2M_P
BA45 MGTYTXN3_124 FMCP_HSPC_DP3_C2M_N A31 DP3_C2M_N
BA49 MGTYRXP3_124 FMCP_HSPC_DP3_M2C_P A10 DP3_M2C_P
BA50 MGTYRXN3_124 FMCP_HSPC_DP3_M2C_N A11 DP3_M2C_N
AV42 MGTREFCLK0P_124 FMCP_HSPC_GBTCLK0_M2C_P
1
D4 GBTCLK0_M2C_P
AV43 MGTREFCLK0N_124 FMCP_HSPC_GBTCLK0_M2C_N
1
D5 GBTCLK0_M2C_N
AT42 MGTREFCLK1P_124
NC NC NC NC
AT43 MGTREFCLK1N_124
Notes:
1. Series 0.01uF capacitor coupled.
Left-side Quads
The four connected GTY Quads on the le side of the XCVU37P FPGA are described in this
secon (MGTY235- MGTY228 are not used).
• Quad 227
○ MGTREFCLK0 - PCIE_CLK2_P/N (U94)
○ MGTREFCLK1 - not connected
○ Four GTY transceivers allocated to PCIe lanes 3:0 PCIE_EP_TX/RX[3:0]
• Quad 226
○ MGTREFCLK0 - not connected
○ MGTREFCLK1 - not connected
Chapter 3: Board Component Descriptions
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 62
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