Xilinx Virtex-5 FPGA ML561

64 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Chapter 7: ML561 Hardware-Simulation Correlation
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Figure 7-10: DDR2 Component Write Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
UG199_c7_10_071007
-100.0
100.0
300.0
500.0
700.0
900.0
1100.0
1300.0
Voltage (mV)
1500.0
1700.0
1900.0
800.0 1200.0 1600.0
Time (ps)
2000.0 2400.0 2800.0
Probe 1:U12.D3 (at die)
♦ 333 MHz, Fast, PRBS6, 92.5% UI
♦ Cursor 1: 701.2 mV, 1.0026 ns
♦ Cursor 2: 774.6 mV, 2.3908 ns
♦ Delta Voltage = 73.4 mV, Delta Time = 1.3883 ns (92.5% UI)
Figure 7-11: DDR2 Component Write Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
65.000 75.000 85.000 95.000 105.000
UG199_c7_11_071007
-100.0
Time (ns)
100.0
300.0
500.0
700.0
Voltage (mV)
900.0
1100.0
1300.0
1500.0
1700.0
1900.0
Probe 1:U12.D3 (at die)