Xilinx Virtex-5 FPGA ML561

68 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Chapter 7: ML561 Hardware-Simulation Correlation
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Figure 7-17: DDR2 Component Read Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
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UG199_c7_17_071007
Time (ps)
Voltage (mV)
Probe 1:U7.P25 (at die)
♦ 333 MHz, Slow, PRBS6, 85.5% UI
♦ Cursor 1: 1.0988V, 1.2170 ns
♦ Cursor 2: 1.0254V, 2.5029 ns
♦ Delta Voltage = 73.4 mV, Delta Time = 1.2859 ns (85.5% UI)
Figure 7-18: DDR2 Component Read Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
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0.000
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Probe 1:U7.P25 (at die)
Voltage (mV)
Time (ns)
UG199_c7_18_071007