Xilinx Virtex-5 FPGA ML561

98 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Appendix A: FPGA Pinouts
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FPGA #1 MII Link Interface
FPGA2_TO_FPGA1_MII_TX_CLK J10 FPGA3_TO_FPGA1_MII_TX_CLK D10
FPGA2_TO_FPGA1_MII_TX_DATA0 C13 FPGA3_TO_FPGA1_MII_TX_DATA0 H10
FPGA2_TO_FPGA1_MII_TX_DATA1 B13 FPGA3_TO_FPGA1_MII_TX_DATA1 C12
FPGA2_TO_FPGA1_MII_TX_DATA2 K9 FPGA3_TO_FPGA1_MII_TX_DATA2 D12
FPGA2_TO_FPGA1_MII_TX_DATA3 K8 FPGA3_TO_FPGA1_MII_TX_DATA3 J11
FPGA2_TO_FPGA1_MII_TX_EN L11 FPGA3_TO_FPGA1_MII_TX_EN A13
FPGA2_TO_FPGA1_MII_TX_ERR L10 FPGA3_TO_FPGA1_MII_TX_ERR H9
FPGA2_TO_FPGA1_MII_TX_SPARE J9 FPGA3_TO_FPGA1_MII_TX_SPARE K11
FPGA #1 Configuration Signals
FPGA_INIT N14 FPGA1_D_IN P15
FPGA_PROGB M22 FPGA1_DONE M15
FPGA_TMS AC14 FPGA1_DOUT_B AD15
FPGA_VBATT L23 FPGA1_HSWAPEN M23
FPGA1_CCLK N15 FPGA1_TCK AB15
FPGA1_CNFG_M0 AD21 FPGA1_TDI_IN AC15
FPGA1_CNFG_M1 AC22 FPGA1_TDO 15 AD14
FPGA1_CNFG_M2 AD22
FPGA #1 Test and Debug Signals
FPGA1_DIP0 AG18 FPGA1_TEST_HDR_BY0_B6 E8
FPGA1_DIP1 AG15 FPGA1_TEST_HDR_BY0_B7 E9
FPGA1_DIP2 AH15 FPGA1_TEST_HDR_BY1_B0 E12
FPGA1_DIP3 AG20 FPGA1_TEST_HDR_BY1_B1 L9
FPGA1_SPYHOLE_BK21 AF26 FPGA1_TEST_HDR_BY1_B2 M10
FPGA1_TEST_HDR_BY0_B0 H8 FPGA1_TEST_HDR_BY1_B3 E11
FPGA1_TEST_HDR_BY0_B1 G8 FPGA1_TEST_HDR_BY1_B4 F11
FPGA1_TEST_HDR_BY0_B2 G10 FPGA1_TEST_HDR_BY1_B5 L8
FPGA1_TEST_HDR_BY0_B3 F10 FPGA1_TEST_HDR_BY1_B6 M8
FPGA1_TEST_HDR_BY0_B4 F8 FPGA1_TEST_HDR_BY1_B7 G12
FPGA1_TEST_HDR_BY0_B5 F9
Table A-1: FPGA #1 Pinout (Continued)
Signal Name Pin Signal Name Pin