Xilinx Virtex-7 FPGA VC7222 IBERT - Page 51

VC7222 IBERT Getting Started Guide www.xilinx.com 51
UG971 (v5.0) June 12, 2014
13. In the Sources window, Design Sources should now reflect that the SuperClock-2
module is part of the example IBERT design (Figure 2-11).
X-Ref Target - Figure 2-11
Figure 2-11: Design Sources File Hierarchy
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