Xilinx Virtex-7 FPGA VC7222 IBERT - Page 50

50 www.xilinx.com VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
Chapter 2: Creating the GTH IBERT Core
12. The SuperClock-2 source code now needs to be added to the example IBERT wrapper.
In the Sources window, double-click example_ibert_7series_gth_0 in the
Design Sources folder to open the verilog code. Add the top level ports from
top_scm2.v to the module declaration, and instantiate the top_scm2 module in the
example ibert wrapper (Figure 2-10). Click File > Save File.
X-Ref Target - Figure 2-10
Figure 2-10: SuperClock-2 in the Example IBERT Wrapper
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