Xilinx Virtex-7 FPGA VC7222 IBERT - Page 59

VC7222 IBERT Getting Started Guide www.xilinx.com 59
UG971 (v5.0) June 12, 2014
5. In the new window select Tools > Run Tcl Script. In the Run Script window,
navigate to add_scm2.tcl in the extracted files and press OK. The SuperClock-2
Module Design Sources and Constraints are added to the example design (Figure 3-6).
X-Ref Target - Figure 3-6
Figure 3-6: Sources after Running add_scm2.tcl
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