Name: Xilinx ZC706
Brand: Xilinx
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ZC706 Evaluation Board User Guide www.xilinx.com 40

UG954 (v1.5) September 10, 2015

Feature Descriptions

• One GTX transceiver is unused and is wired in a capacitively coupled TX-to-RX loopback

configuration

The GTX transceivers in Zynq-7000 series AP SoCs are grouped into four channels described

as Quads. The reference clock for a Quad can be sourced from the Quad above or Quad

below the GTX Quad of interest. There are four GTX Quads on the ZC706 board with

connectivity as shown here:

• Quad 109:

MGTREFCLK0 - FMC_HPC_GBTCLK0_M2C clock

MGTREFCLK1 - not connected

Contains 4 GTX transceivers allocated to FMC_HPC_DP[3:0]_C2M_P/N

• Quad 110:

MGTREFCLK0 - FMC_HPC_GBTCLK1_M2C clock

MGTREFCLK1 - SI5324_OUT_C_P/N jitter attenuator clock

Contains 4 GTX transceivers allocated to FMC_HPC_DP[7:4]_C2M_P/N

• Quad 111:

MGTREFCLK0 - FMC_LPC_GBTCLK0_M2C_C_P/N

MGTREFCLK1 - SMA_MGT_REFCLK_P/N SMA GTX clock input

Contains 1 GTX transceiver allocated to FMC_LPC_DP0_C2M_P/N

Contains 1 GTX transceiver allocated to SMA_MGT_TX_P/N and RX_P/N SMA

connectors

Contains 1 GTX transceiver allocated to SFP_TX and _RX_P/N SFP/SFP+ connector

Contains 1 GTX transceiver which is unused and is wired in TX-to-RX loopback

configuration

• Quad 112:

MGTREFCLK0 - PCIE_CLK_Q0_P/N PCIe edge connector clock

MGTREFCLK1 - not connected

Contains 4 GTX transceivers allocated to PCIe lanes 0-3

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