Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 120
UG1182 (v1.2) March 20, 2017
Appendix B: Master Constraints File Listing
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA1"]
set_property PACKAGE_PIN AK4 [get_ports "DDR4_DQ0"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ0"]
set_property PACKAGE_PIN AK5 [get_ports "DDR4_DQ1"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ1"]
set_property PACKAGE_PIN AN4 [get_ports "DDR4_DQ2"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ2"]
set_property PACKAGE_PIN AM4 [get_ports "DDR4_DQ3"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ3"]
set_property PACKAGE_PIN AP4 [get_ports "DDR4_DQ4"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ4"]
set_property PACKAGE_PIN AP5 [get_ports "DDR4_DQ5"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ5"]
set_property PACKAGE_PIN AM5 [get_ports "DDR4_DQ6"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ6"]
set_property PACKAGE_PIN AM6 [get_ports "DDR4_DQ7"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ7"]
set_property PACKAGE_PIN AK2 [get_ports "DDR4_DQ8"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ8"]
set_property PACKAGE_PIN AK3 [get_ports "DDR4_DQ9"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ9"]
set_property PACKAGE_PIN AL1 [get_ports "DDR4_DQ10"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ10"]
set_property PACKAGE_PINAK1 [get_ports "DDR4_DQ11"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ11"]
set_property PACKAGE_PIN AN1 [get_ports "DDR4_DQ12"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ12"]
set_property PACKAGE_PIN AM1 [get_ports "DDR4_DQ13"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ13"]
set_property PACKAGE_PIN AP3 [get_ports "DDR4_DQ14"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ14"]
set_property PACKAGE_PIN AN3 [get_ports "DDR4_DQ15"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ15"]
set_property PACKAGE_PIN AP6 [get_ports "DDR4_DQS0_C"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS0_C"]
set_property PACKAGE_PIN AN6 [get_ports "DDR4_DQS0_T"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS0_T"]
set_property PACKAGE_PIN AL2 [get_ports "DDR4_DQS1_C"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS1_C"]
set_property PACKAGE_PIN AL3 [get_ports "DDR4_DQS1_T"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS1_T"]
set_property PACKAGE_PIN AL6 [get_ports "DDR4_DM0"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM0"]
set_property PACKAGE_PIN AN2 [get_ports "DDR4_DM1"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM1"]
set_property PACKAGE_PIN AP7 [get_ports "DDR4_CK_C"]
set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CK_C"]
set_property PACKAGE_PIN AN7 [get_ports "DDR4_CK_T"]
set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CK_T"]
set_property PACKAGE_PIN AM3 [get_ports "DDR4_CKE"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CKE"]
set_property PACKAGE_PIN AK7 [get_ports "DDR4_BG0"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BG0"]
set_property PACKAGE_PIN AP1 [get_ports "DDR4_PAR"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_PAR"]
set_property PACKAGE_PIN AK8 [get_ports "DDR4_ACT_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ACT_B"]
set_property PACKAGE_PIN AK9 [get_ports "DDR4_ODT"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ODT"]
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux