Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 121
UG1182 (v1.2) March 20, 2017
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN AH9 [gt_ports "DDR4_RESET_B_LS"]
set_property IOSTANDARD LVCMOS18 [gt_ports "DDR4_RESET_B_LS"]
set_property PACKAGE_PINAP2 [get_ports "DDR4_CS_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CS_B"]
#QSPI
#QSPI_LWR U119 and UPR U120 are connected to PS MIO Bank 500
#Other net PACKAGE_PIN AF16 - MIO0_QSPI_LWR_CLK Bank 500
#Other net PACKAGE_PIN AJ16 - MIO1_QSPI_LWR_DQ1 Bank 500
#Other net PACKAGE_PIN AD16 - MIO2_QSPI_LWR_DQ2 Bank 500
#Other net PACKAGE_PIN AG16 - MIO3_QSPI_LWR_DQ3 Bank 500
#Other net PACKAGE_PIN AH16 - MIO4_QSPI_LWR_DQ0 Bank 500
#Other net PACKAGE_PIN AM15 - MIO5_QSPI_LWR_CS_B Bank 500
#Other net PACKAGE_PIN AD17 - MIO7_QSPI_UPR_CS_B Bank 500
#Other net PACKAGE_PIN AE17 - MIO8_QSPI_UPR_DQ0 Bank 500
#Other net PACKAGE_PIN AP15 - MIO9_QSPI_UPR_DQ1 Bank 500
#Other net PACKAGE_PIN AH17 - MIO10_QSPI_UPR_DQ2 Bank 500
#Other net PACKAGE_PIN AF17 - MIO11_QSPI_UPR_DQ3 Bank 500
#Other net PACKAGE_PIN AJ17 - MIO12_QSPI_UPR_CLK Bank 500
#FMC
#HPC0 J5
set_property PACKAGE_PIN AA6 [get_ports "FMC_HPC0_CLK0_M2C_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK0_M2C_N"]
set_property PACKAGE_PIN AA7 [get_ports "FMC_HPC0_CLK0_M2C_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK0_M2C_P"]
set_property PACKAGE_PIN R8 [get_ports "FMC_HPC0_CLK1_M2C_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK1_M2C_N"]
set_property PACKAGE_PIN T8 [get_ports "FMC_HPC0_CLK1_M2C_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK1_M2C_P"]
set_property PACKAGE_PIN G7 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_N"]
set_property PACKAGE_PIN G8 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_P"]
set_property PACKAGE_PIN L7 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_N"]
set_property PACKAGE_PIN L8 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_P"]
set_property PACKAGE_PIN G3 [get_ports "FMC_HPC0_DP0_C2M_N"]
set_property PACKAGE_PIN G4 [get_ports "FMC_HPC0_DP0_C2M_P"]
set_property PACKAGE_PIN H1 [get_ports "FMC_HPC0_DP0_M2C_N"]
set_property PACKAGE_PIN H2 [get_ports "FMC_HPC0_DP0_M2C_P"]
set_property PACKAGE_PIN H5 [get_ports "FMC_HPC0_DP1_C2M_N"]
set_property PACKAGE_PIN H6 [get_ports "FMC_HPC0_DP1_C2M_P"]
set_property PACKAGE_PIN J3 [get_ports "FMC_HPC0_DP1_M2C_N"]
set_property PACKAGE_PIN J4 [get_ports "FMC_HPC0_DP1_M2C_P"]
set_property PACKAGE_PIN F5 [get_ports "FMC_HPC0_DP2_C2M_N"]
set_property PACKAGE_PIN F6 [get_ports "FMC_HPC0_DP2_C2M_P"]
set_property PACKAGE_PIN F1 [get_ports "FMC_HPC0_DP2_M2C_N"]
set_property PACKAGE_PIN F2 [get_ports "FMC_HPC0_DP2_M2C_P"]
set_property PACKAGE_PIN K5 [get_ports "FMC_HPC0_DP3_C2M_N"]
set_property PACKAGE_PIN K6 [get_ports "FMC_HPC0_DP3_C2M_P"]
set_property PACKAGE_PIN K1 [get_ports "FMC_HPC0_DP3_M2C_N"]
set_property PACKAGE_PIN K2 [get_ports "FMC_HPC0_DP3_M2C_P"]
set_property PACKAGE_PIN M5 [get_ports "FMC_HPC0_DP4_C2M_N"]
set_property PACKAGE_PIN M6 [get_ports "FMC_HPC0_DP4_C2M_P"]
set_property PACKAGE_PIN L3 [get_ports "FMC_HPC0_DP4_M2C_N"]
set_property PACKAGE_PIN L4 [get_ports "FMC_HPC0_DP4_M2C_P"]
set_property PACKAGE_PIN P5 [get_ports "FMC_HPC0_DP5_C2M_N"]
set_property PACKAGE_PIN P6 [get_ports "FMC_HPC0_DP5_C2M_P"]
set_property PACKAGE_PIN P1 [get_ports "FMC_HPC0_DP5_M2C_N"]
set_property PACKAGE_PIN P2 [get_ports "FMC_HPC0_DP5_M2C_P"]
set_property PACKAGE_PIN R3 [get_ports "FMC_HPC0_DP6_C2M_N"]
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux