Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 127
UG1182 (v1.2) March 20, 2017
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN T12 [get_ports "FMC_HPC1_LA26_P"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA26_P"]
set_property PACKAGE_PIN T10 [get_ports "FMC_HPC1_LA27_N"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA27_N"]
set_property PACKAGE_PIN U10 [get_ports "FMC_HPC1_LA27_P"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA27_P"]
set_property PACKAGE_PIN R13 [get_ports "FMC_HPC1_LA28_N"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA28_N"]
set_property PACKAGE_PIN T13 [get_ports "FMC_HPC1_LA28_P"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA28_P"]
set_property PACKAGE_PIN W11 [get_ports "FMC_HPC1_LA29_N"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA29_N"]
set_property PACKAGE_PIN W12 [get_ports "FMC_HPC1_LA29_P"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA29_P"]
#HDMI
set_property PACKAGE_PIN T34 [get_ports "HDMI_RX0_C_N"]
set_property PACKAGE_PIN T33 [get_ports "HDMI_RX0_C_P"]
set_property PACKAGE_PIN P34 [get_ports "HDMI_RX1_C_N"]
set_property PACKAGE_PIN P33 [get_ports "HDMI_RX1_C_P"]
set_property PACKAGE_PIN N32 [get_ports "HDMI_RX2_C_N"]
set_property PACKAGE_PIN N31 [get_ports "HDMI_RX2_C_P"]
set_property PACKAGE_PIN T30 [get_ports "HDMI_TX0_N"]
set_property PACKAGE_PIN T29 [get_ports "HDMI_TX0_P"]
set_property PACKAGE_PIN R32 [get_ports "HDMI_TX1_N"]
set_property PACKAGE_PIN R31 [get_ports "HDMI_TX1_P"]
set_property PACKAGE_PIN P30 [get_ports "HDMI_TX2_N"]
set_property PACKAGE_PIN P29 [get_ports "HDMI_TX2_P"]
set_property PACKAGE_PIN R28 [get_ports "HDMI_SI5324_OUT_C_N"]
set_property PACKAGE_PIN R27 [get_ports "HDMI_SI5324_OUT_C_P"]
set_property PACKAGE_PIN AG4 [get_ports "HDMI_REC_CLOCK_C_N"]
set_property IOSTANDARD LVDS [get_ports "HDMI_REC_CLOCK_C_N"]
set_property PACKAGE_PIN AG5 [get_ports "HDMI_REC_CLOCK_C_P"]
set_property IOSTANDARD LVDS [get_ports "HDMI_REC_CLOCK_C_P"]
set_property PACKAGE_PIN AG6 [get_ports "HDMI_TX_LVDS_OUT_N"]
set_property IOSTANDARD LVDS [get_ports "HDMI_TX_LVDS_OUT_N"]
set_property PACKAGE_PIN AF6 [get_ports "HDMI_TX_LVDS_OUT_P"]
set_property IOSTANDARD LVDS [get_ports "HDMI_TX_LVDS_OUT_P"]
set_property PACKAGE_PIN N28 [get_ports "HDMI_RX_CLK_C_N"]
set_property PACKAGE_PIN N27 [get_ports "HDMI_RX_CLK_C_P"]
set_property PACKAGE_PIN D14 [get_ports "HDMI_RX_PWR_DET"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_PWR_DET"]
set_property PACKAGE_PIN E14 [get_ports "HDMI_RX_HPD"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_HPD"]
set_property PACKAGE_PIN D15 [get_ports "HDMI_RX_CEC_SINK"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_CEC_SINK"]
set_property PACKAGE_PIN E15 [get_ports "HDMI_RX_SNK_SCL"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_SNK_SCL"]
set_property PACKAGE_PIN A15 [get_ports "HDMI_RX_SNK_SDA"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_SNK_SDA"]
set_property PACKAGE_PIN B15 [get_ports "HDMI_TX_EN"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_EN"]
set_property PACKAGE_PIN A16 [get_ports "HDMI_TX_CEC"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_CEC"]
set_property PACKAGE_PIN B16 [get_ports "HDMI_TX_HPD"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_HPD"]
set_property PACKAGE_PIN C16 [get_ports "HDMI_TX_SRC_SCL"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_SRC_SCL"]
set_property PACKAGE_PIN D16 [get_ports "HDMI_TX_SRC_SDA"]
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux