Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 128
UG1182 (v1.2) March 20, 2017
Appendix B: Master Constraints File Listing
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_SRC_SDA"]
set_property PACKAGE_PIN F15 [get_ports "HDMI_CTL_SCL"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_CTL_SCL"]
set_property PACKAGE_PIN F16 [get_ports "HDMI_CTL_SDA"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_CTL_SDA"]
set_property PACKAGE_PIN H12 [get_ports "HDMI_SI5324_LOL"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_LOL"]
set_property PACKAGE_PIN J12 [get_ports "HDMI_SI5324_RST"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_RST"]
set_property PACKAGE_PIN F11 [get_ports "HDMI_SI5324_INT_ALM"]
set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_INT_ALM"]
#ARM TRACE
set_property PACKAGE_PIN A18 [get_ports "TRACEDBGRQ"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDBGRQ"]
set_property PACKAGE_PIN A17 [get_ports "TRACESRST_B"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACESRST_B"]
set_property PACKAGE_PIN C19 [get_ports "TRACETDO"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACETDO"]
set_property PACKAGE_PIN C18 [get_ports "TRACERTCK"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACERTCK"]
set_property PACKAGE_PIN B19 [get_ports "TRACETCK"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACETCK"]
set_property PACKAGE_PIN B18 [get_ports "TRACETMS"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACETMS"]
set_property PACKAGE_PIN C17 [get_ports "TRACETDI"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACETDI"]
set_property PACKAGE_PIN D17 [get_ports "TRACETRST_B"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACETRST_B"]
set_property PACKAGE_PIN E18 [get_ports "TRACEDATA15"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA15"]
set_property PACKAGE_PIN E17 [get_ports "TRACEDATA14"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA14"]
set_property PACKAGE_PIN D19 [get_ports "TRACEDATA13"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA13"]
set_property PACKAGE_PIN E19 [get_ports "TRACEDATA12"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA12"]
set_property PACKAGE_PIN F18 [get_ports "TRACEDATA11"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA11"]
set_property PACKAGE_PIN F17 [get_ports "TRACEDATA10"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA10"]
set_property PACKAGE_PIN G19 [get_ports "TRACEDATA9"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA9"]
set_property PACKAGE_PIN G18 [get_ports "TRACEDATA8"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA8"]
set_property PACKAGE_PIN K17 [get_ports "TRACECLKA"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACECLKA"]
set_property PACKAGE_PIN L17 [get_ports "TRACEDBGACK"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDBGACK"]
set_property PACKAGE_PIN K18 [get_ports "TRACEEXTTRIG"
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEEXTTRIG"
set_property PACKAGE_PIN L18 [get_ports "TRACEDATA7"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA7"]
set_property PACKAGE_PIN H17 [get_ports "TRACEDATA6"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA6"]
set_property PACKAGE_PIN J17 [get_ports "TRACEDATA5"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA5"]
set_property PACKAGE_PIN H19 [get_ports "TRACEDATA4"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA4"]
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux