Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 129
UG1182 (v1.2) March 20, 2017
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN H18 [get_ports "TRACEDATA3"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA3"]
set_property PACKAGE_PIN H21 [get_ports "TRACEDATA2"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA2"]
set_property PACKAGE_PIN J21 [get_ports "TRACEDATA1"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA1"]
set_property PACKAGE_PIN K19 [get_ports "TRACECTL"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACECTL"]
set_property PACKAGE_PIN L19 [get_ports "TRACEDATA0"]
set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA0"]
#GPIO
#PUSHBUTTON SWITCHES
set_property PACKAGE_PIN AE14 [get_ports "GPIO_SW_E"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_E"]
set_property PACKAGE_PIN AE15 [get_ports "GPIO_SW_S"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_S"]
set_property PACKAGE_PIN AG15 [get_ports "GPIO_SW_N"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_N"]
set_property PACKAGE_PIN AF15 [get_ports "GPIO_SW_W"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_W"]
set_property PACKAGE_PIN AG13 [get_ports "GPIO_SW_C"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_C"]
#CPU RESET PUSHBUTTON
set_property PACKAGE_PIN AM13 [get_ports "CPU_RESET"]
set_property IOSTANDARD LVCMOS33 [get_ports "CPU_RESET"]
#DIP SWITCH 8-POLE
set_property PACKAGE_PIN AK13 [get_ports "GPIO_DIP_SW7"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW7"]
set_property PACKAGE_PIN AL13 [get_ports "GPIO_DIP_SW6"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW6"]
set_property PACKAGE_PIN AP12 [get_ports "GPIO_DIP_SW5"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW5"]
set_property PACKAGE_PIN AN12 [get_ports "GPIO_DIP_SW4"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW4"]
set_property PACKAGE_PIN AN13 [get_ports "GPIO_DIP_SW3"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW3"]
set_property PACKAGE_PIN AM14 [get_ports "GPIO_DIP_SW2"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW2"]
set_property PACKAGE_PIN AP14 [get_ports "GPIO_DIP_SW1"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW1"]
set_property PACKAGE_PIN AN14 [get_ports "GPIO_DIP_SW0"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW0"]
#LED
set_property PACKAGE_PIN AG14 [get_ports "GPIO_LED_0"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_0"]
set_property PACKAGE_PIN AF13 [get_ports "GPIO_LED_1"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_1"]
set_property PACKAGE_PIN AE13 [get_ports "GPIO_LED_2"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_2"]
set_property PACKAGE_PIN AJ14 [get_ports "GPIO_LED_3"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_3"]
set_property PACKAGE_PIN AJ15 [get_ports "GPIO_LED_4"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_4"]
set_property PACKAGE_PIN AH13 [get_ports "GPIO_LED_5"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_5"]
Send Feedback

Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux