Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 130
UG1182 (v1.2) March 20, 2017
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN AH14 [get_ports "GPIO_LED_6"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_6"]
set_property PACKAGE_PIN AL12 [get_ports "GPIO_LED_7"]
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_7"]
#PMOD
#PMOD0 RT. ANGLE RECEPTACLE 2X6
set_property PACKAGE_PIN A20 [get_ports "PMOD0_0"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_0"]
set_property PACKAGE_PIN B20 [get_ports "PMOD0_1"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_1"]
set_property PACKAGE_PIN A22 [get_ports "PMOD0_2"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_2"]
set_property PACKAGE_PIN A21 [get_ports "PMOD0_3"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_3"]
set_property PACKAGE_PIN B21 [get_ports "PMOD0_4"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_4"]
set_property PACKAGE_PIN C21 [get_ports "PMOD0_5"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_5"]
set_property PACKAGE_PIN C22 [get_ports "PMOD0_6"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_6"]
set_property PACKAGE_PIN D21 [get_ports "PMOD0_7"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_7"]
#PMOD1 MALE PIN HEADER 2X6
set_property PACKAGE_PIN D20 [get_ports "PMOD1_0"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_0"]
set_property PACKAGE_PIN E20 [get_ports "PMOD1_1"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_1"]
set_property PACKAGE_PIN D22 [get_ports "PMOD1_2"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_2"]
set_property PACKAGE_PIN E22 [get_ports "PMOD1_3"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_3"]
set_property PACKAGE_PIN F20 [get_ports "PMOD1_4"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_4"]
set_property PACKAGE_PIN G20 [get_ports "PMOD1_5"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_5"]
set_property PACKAGE_PIN J20 [get_ports "PMOD1_6"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_6"]
set_property PACKAGE_PIN J19 [get_ports "PMOD1_7"]
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_7"]
#PROTOTYPE HEADER J3 MALE PIN HEADER 2X12
set_property PACKAGE_PIN J15 [get_ports "L12N_AD8N_50_N"]
set_property IOSTANDARD LVCMOS33 [get_ports "L12N_AD8N_50_N"]
set_property PACKAGE_PIN J16 [get_ports "L12P_AD8P_50_P"]
set_property IOSTANDARD LVCMOS33 [get_ports "L12P_AD8P_50_P"]
set_property PACKAGE_PIN G16 [get_ports "L11N_AD9N_50_N"]
set_property IOSTANDARD LVCMOS33 [get_ports "L11N_AD9N_50_N"]
set_property PACKAGE_PIN H16 [get_ports "L11P_AD9P_50_P"]
set_property IOSTANDARD LVCMOS33 [get_ports "L11P_AD9P_50_P"]
set_property PACKAGE_PIN H14 [get_ports "L10N_AD10N_50_N"]
set_property IOSTANDARD LVCMOS33 [get_ports "L10N_AD10N_50_N"]
set_property PACKAGE_PIN J14 [get_ports "L10P_AD10P_50_P"]
set_property IOSTANDARD LVCMOS33 [get_ports "L10P_AD10P_50_P"]
set_property PACKAGE_PIN G14 [get_ports "L9N_AD11N_50_N"]
set_property IOSTANDARD LVCMOS33 [get_ports "L9N_AD11N_50_N"]
set_property PACKAGE_PIN G15 [get_ports "L9P_AD11P_50_P"]
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux