Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 131
UG1182 (v1.2) March 20, 2017
Appendix B: Master Constraints File Listing
set_property IOSTANDARD LVCMOS33 [get_ports "L9P_AD11P_50_P"]
set_property PACKAGE_PIN G13 [get_ports "L8N_HDGC_50_N"]
set_property IOSTANDARD LVCMOS33 [get_ports "L8N_HDGC_50_N"]
set_property PACKAGE_PIN H13 [get_ports "L8P_HDGC_50_P"]
set_property IOSTANDARD LVCMOS33 [get_ports "L8P_HDGC_50_P"]
#MSP430 SYSTEM CONTROLLER
set_property PACKAGE_PIN D11 [get_ports "MSP430_GPIO_PL_0"]
set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_0"]
set_property PACKAGE_PIN E10 [get_ports "MSP430_GPIO_PL_1"]
set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_1"]
set_property PACKAGE_PIN F10 [get_ports "MSP430_GPIO_PL_2"]
set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_2"]
set_property PACKAGE_PIN G10 [get_ports "MSP430_GPIO_PL_3"]
set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_3"]
set_property PACKAGE_PIN B12 [get_ports "MSP430_UCA1_TXD"]
set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_UCA1_TXD"]
set_property PACKAGE_PIN C12 [get_ports "MSP430_UCA1_RXD"]
set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_UCA1_RXD"]
#SFP
#SFP0
set_property PACKAGE_PIN D1[get_ports "SFP0_RX_N"]
set_property PACKAGE_PIN D2[get_ports "SFP0_RX_P"]
set_property PACKAGE_PIN E3[get_ports "SFP0_TX_N"]
set_property PACKAGE_PIN E4[get_ports "SFP0_TX_P"]
set_property PACKAGE_PIN A12[get_ports "SFP0_TX_DISABLE"]
set_property IOSTANDARDLVCMOS33 [get_ports "SFP0_TX_DISABLE"]
#SFP1
set_property PACKAGE_PIN C3[get_ports "SFP1_RX_N"]
set_property PACKAGE_PIN C4[get_ports "SFP1_RX_P"]
set_property PACKAGE_PIN D5[get_ports "SFP1_TX_N"]
set_property PACKAGE_PIN D6[get_ports "SFP1_TX_P"]
set_property PACKAGE_PIN A13[get_ports "SFP1_TX_DISABLE"]
set_property IOSTANDARDLVCMOS33 [get_ports "SFP1_TX_DISABLE"]
#SFP2
set_property PACKAGE_PIN B1[get_ports "SFP2_RX_N"]
set_property PACKAGE_PIN B2[get_ports "SFP2_RX_P"]
set_property PACKAGE_PIN B5[get_ports "SFP2_TX_N"]
set_property PACKAGE_PIN B6[get_ports "SFP2_TX_P"]
set_property PACKAGE_PIN B13[get_ports "SFP2_TX_DISABLE"]
set_property IOSTANDARDLVCMOS33 [get_ports "SFP2_TX_DISABLE"]
#SFP3
set_property PACKAGE_PIN A3[get_ports "SFP3_RX_N"]
set_property PACKAGE_PIN A4[get_ports "SFP3_RX_P"]
set_property PACKAGE_PIN A7[get_ports "SFP3_TX_N"]
set_property PACKAGE_PIN A8[get_ports "SFP3_TX_P"]
set_property PACKAGE_PIN C13[get_ports "SFP3_TX_DISABLE"]
set_property IOSTANDARDLVCMOS33 [get_ports "SFP3_TX_DISABLE"]
#SFP COMMON
set_property PACKAGE_PIN R9[get_ports "SFP_REC_CLOCK_C_N"]
set_property IOSTANDARDLVDS[get_ports "SFP_REC_CLOCK_C_N"]
set_property PACKAGE_PIN R10[get_ports "SFP_REC_CLOCK_C_P"]
set_property IOSTANDARDLVDS[get_ports "SFP_REC_CLOCK_C_P"]
set_property PACKAGE_PIN B9[get_ports "SFP_SI5328_OUT_C_N"]
Send Feedback

Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux