Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 132
UG1182 (v1.2) March 20, 2017
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN B10[get_ports "SFP_SI5328_OUT_C_P"]
set_property PACKAGE_PIN H10[get_ports "SFP_SI5328_INT_ALM"]
set_property IOSTANDARDLVCMOS33 [get_ports "SFP_SI5328_INT_ALM"]
#I2C BUS
#I2C0
set_property PACKAGE_PIN J10 [get_ports "PL_I2C0_SCL_LS"]
set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C0_SCL_LS"]
set_property PACKAGE_PIN J11 [get_ports "PL_I2C0_SDA_LS"]
set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C0_SDA_LS"]
#I2C1
set_property PACKAGE_PIN K20 [get_ports "PL_I2C1_SCL_LS"]
set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C1_SCL_LS"]
set_property PACKAGE_PIN L20 [get_ports "PL_I2C1_SDA_LS"]
set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C1_SDA_LS"]
#SYSMON I2C
set_property PACKAGE_PIN B14 [get_ports "SYSMON_SDA"]
set_property IOSTANDARD LVCMOS33 [get_ports "SYSMON_SDA"]
set_property PACKAGE_PIN C14 [get_ports "SYSMON_SCL"]
set_property IOSTANDARD LVCMOS33 [get_ports "SYSMON_SCL"]
#DISPLAY PORT
set_property PACKAGE_PIN F12 [get_ports "PL_DPAUX_IN"]
set_property IOSTANDARD LVCMOS33 [get_ports "PL_DPAUX_IN"]
set_property PACKAGE_PIN G11 [get_ports "PL_DP_OE"]
set_property IOSTANDARD LVCMOS33 [get_ports "PL_DP_OE"]
set_property PACKAGE_PIN H11 [get_ports "PL_DP_HPD"]
set_property IOSTANDARD LVCMOS33 [get_ports "PL_DP_HPD"]
set_property PACKAGE_PIN D10 [get_ports "PL_DPAUX_OUT"]
set_property IOSTANDARD LVCMOS33 [get_ports "PL_DPAUX_OUT"]
#USER MGT I/O
set_property PACKAGE_PIN M34 [get_ports "SMA_MGT_RX_C_N"]
set_property PACKAGE_PIN M33 [get_ports "SMA_MGT_RX_C_P"]
set_property PACKAGE_PIN M30 [get_ports "SMA_MGT_TX_N"]
set_property PACKAGE_PIN M29 [get_ports "SMA_MGT_TX_P"]
#USER MGT CLOCK
set_property PACKAGE_PIN J28 [get_ports "USER_SMA_MGT_CLOCK_C_N"]
set_property PACKAGE_PIN J27 [get_ports "USER_SMA_MGT_CLOCK_C_P"]
set_property PACKAGE_PIN L28 [get_ports "USER_MGT_SI570_CLOCK1_C_N"]
set_property PACKAGE_PIN L27 [get_ports "USER_MGT_SI570_CLOCK1_C_P"]
set_property PACKAGE_PIN C7 [get_ports "USER_MGT_SI570_CLOCK2_C_N"]
set_property PACKAGE_PIN C8 [get_ports "USER_MGT_SI570_CLOCK2_C_P"]
#UART
set_property PACKAGE_PIN E13 [get_ports "UART2_TXD_O_FPGA_RXD"]
set_property IOSTANDARD LVCMOS33 [get_ports "UART2_TXD_O_FPGA_RXD"]
set_property PACKAGE_PIN F13 [get_ports "UART2_RXD_I_FPGA_TXD"]
set_property IOSTANDARD LVCMOS33 [get_ports "UART2_RXD_I_FPGA_TXD"]
set_property PACKAGE_PIN D12 [get_ports "UART2_RTS_O_B"]
set_property IOSTANDARD LVCMOS33 [get_ports "UART2_RTS_O_B"]
set_property PACKAGE_PIN E12 [get_ports "UART2_CTS_I_B"]
set_property IOSTANDARD LVCMOS33 [get_ports "UART2_CTS_I_B"]
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux