ZCU102 Evaluation Board User Guide www.xilinx.com 25
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
The ZCU102 supports full power-off suspend mode where only the system controller and
the PS-side DDR4 SODIMM memory are powered. The DDR4 memory is kept in a
self-refresh state and has its reset input controlled by the system controller such that the
memory is not reset when waking-up from suspend mode. DDR4 SODIMM standard right
angle Socket J1 connections are identified in Table 3-3.
Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504
XCZU9EG
(U1) Pin
Net Name
DDR4 SODIMM Memory J1
Pin Number Pin Name
AP29
DDR4_SODIMM_A0 144 A0
AP30
DDR4_SODIMM_A1 133 A1
AP26
DDR4_SODIMM_A2 132 A2
AP27
DDR4_SODIMM_A3 131 A3
AP25
DDR4_SODIMM_A4 128 A4
AN24
DDR4_SODIMM_A5 126 A5
AM29
DDR4_SODIMM_A6 127 A6
AM28
DDR4_SODIMM_A7 122 A7
AM26
DDR4_SODIMM_A8 125 A8
AM25
DDR4_SODIMM_A9 121 A9
AL28
DDR4_SODIMM_A10 146 A10/AP
AK27
DDR4_SODIMM_A11 120 A11
AJ25
DDR4_SODIMM_A12 119 A12
AL25
DDR4_SODIMM_A13 158 A13
AH26
DDR4_SODIMM_BA0 150 BA0
AG26
DDR4_SODIMM_BA1 145 BA1
AK28
DDR4_SODIMM_BG0 115 BG0
AH27
DDR4_SODIMM_BG1 113 BG1
AP20
DDR4_SODIMM_DQ0 8 DQ0
AP18
DDR4_SODIMM_DQ1 7 DQ1
AP19
DDR4_SODIMM_DQ2 20 DQ2
AP17
DDR4_SODIMM_DQ3 21 DQ3
AM20
DDR4_SODIMM_DQ4 4 DQ4
AM19
DDR4_SODIMM_DQ5 3 DQ5
AM18
DDR4_SODIMM_DQ6 16 DQ6
AL18
DDR4_SODIMM_DQ7 17 DQ7
AP22
DDR4_SODIMM_DQ8 28 DQ8
AP21
DDR4_SODIMM_DQ9 29 DQ9
AP24
DDR4_SODIMM_DQ10 41 DQ10
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