Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 31
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
Note: The ZCU102 board DDR4 16-bit component memory interface adheres to the constraints
guidelines documented in the PCB Guidelines for DDR4 section of UltraScale Architecture PCB Design
User Guide (UG583) [Ref 3]. The ZCU102 DDR4 component interface is a 40Ω impedance
implementations. Other memory interface details are also available in the UltraScale Architecture
FPGAs Memory Interface Solutions Product Guide (PG150) [Ref 4]. For more details, see the Micron
MT40A256M16GE-075E data sheet at the Micron website [Ref 13].
AL6
DDR4_DM0 POD12_DCI E7 DML_B/DBIL_B
AN2
DDR4_DM1 POD12_DCI E2 DMU_B/DBIU_B
Table 3-4: DDR4 Component Memory Connection to the XCZU9EG MPSoC (Cont’d)
XCZU9EG
(U1) Pin
Net Name I/O Standard
DDR4 Component Memory
Pin Number Pin Name
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux