Xilinx ZCU102

ZCU102 Evaluation Board User Guide www.xilinx.com 42
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
The P6 connector to MPSoC connections are listed in Table 3-11.
For more information about managing the Zynq MPSoC extended MIO (EMIO) trace port
connections refer to the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085)
[Ref 2].
Table 3-11: Trace/Debug Conn. P6 Connections to the XCZU9EG MPSoC
XCZU9EG (U1)
Pin
Schematic Net
Name
I/O Standard
Trace/Debug P6
Pin
L19
TRACEDATA0
LVCMOS33 38
J21
TRACEDATA1
LVCMOS33 28
H21
TRACEDATA2
LVCMOS33 26
H18
TRACEDATA3
LVCMOS33 24
H19
TRACEDATA4
LVCMOS33 22
J17
TRACEDATA5
LVCMOS33 20
H17
TRACEDATA6
LVCMOS33 18
L18
TRACEDATA7
LVCMOS33 16
G18
TRACEDATA8
LVCMOS33 37
G19
TRACEDATA9
LVCMOS33 35
F17
TRACEDATA1
LVCMOS33 33
F18
TRACEDATA11
LVCMOS33 31
E19
TRACEDATA12
LVCMOS33 29
D19
TRACEDATA13
LVCMOS33 27
E17
TRACEDATA14
LVCMOS33 25
E18
TRACEDATA15
LVCMOS33 23
K17
TRACECLKA
LVCMOS33 6
C18
TRACERTCK
LVCMOS33 13
A18
TRACEDBGRQ
LVCMOS33 7
L17
TRACEDBGACK
LVCMOS33 8
K19
TRACECTL
LVCMOS33 36
K18
TRACEEXTTRIG
LVCMOS33 10
B19
TRACETCK
LVCMOS33 15
C17
TRACETDI
LVCMOS33 19
C19
TRACETDO
LVCMOS33 11
B18
TRACETMS
LVCMOS33 17
D17
TRACETRST_B
LVCMOS33 21
A17
TRACESRST_B
LVCMOS33 9
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