Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 52
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
CP2108 Channel 2 PL-Side UART Interface
The CP2108 channel 2 PL-side UART interface circuit is shown in Figure 3-15. The
connections from XCZU9EG MPSoC U1 to CP2108 U40 via TSX0104E level shifter U52 are
listed in Table 3-16.
X-Ref Target - Figure 3-15
Figure 3-15: PL-Side USB UART Interface
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Table 3-16: XCZU9EG U1 to CP2108 U40 Connections via L/S U52
XCZU9EG (U1)
Pin
Schematic Net Name
CP2108 U40
Pin Name Pin No.
E13
UART2_TXD_O_FPGA_RXD TX_2
16
F13
UART2_RXD_I_FPGA_TXD RX_2
15
D12
UART2_RTS_O_B RTS_2
14
E12
UART2_CTS_I_B CTS_2
13
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux