Xilinx ZCU102

ZCU102 Evaluation Board User Guide www.xilinx.com 66
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
X-Ref Target - Figure 3-24
Figure 3-24: HDMI Interface Circuit
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Table 3-29: HDMI Retimer U94 Connections to FPGA U1
XCZU9EG
(U1) Pin
Schematic Net Name I/O Standard
Connected Component
Pin No. Pin Name Device
T29
HDMI_TX0_P
(1)
8
IN_D0P
SN65DP159
(U94)
T30
HDMI_TX0_N
(1)
9
IN_D0N
R31
HDMI_TX1_P
(1)
5
IN_D1P
R32
HDMI_TX1_N
(1)
6
IN_D1N
P29
HDMI_TX2_P
(1)
2
IN_D2P
P30
HDMI_TX2_N
(1)
3
IN_D2N
AF6
HDMI_TX_LVDS_OUT_P
LVDS 11
IN_CLKP
AG6
HDMI_TX_LVDS_OUT_N
LVDS 12
IN_CLKN
C16
HDMI_TX_SRC_SCL
LVCMOS33 46
SCL_SRC
D16
HDMI_TX_SRC_SDA
LVCMOS33 47
SDA_SRC
B15
HDMI_TX_EN
LVCMOS33 42
OE
F15
HDMI_CTL_SCL
LVCMOS33 15
SCL_CTL
(2)
F16
HDMI_CTL_SDA
LVCMOS33 16
SDA_CTL
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