Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 65
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
16-bit color depth at 1080p (1920 x 1080 / 60 Hz). The SN65DP159RGZ device can
automatically configure itself as a re-driver at data rates <1 Gb/s, or as a re-timer at more
than this data rate. This feature can be turned off through I2C programming.
The HDMI video output block diagram is shown in Figure 3-23, the interface circuit in
Figure 3-24. The connections between the codec and the XCZU9EG MPSoC are listed in
Table 3-29.
X-Ref Target - Figure 3-23
Figure 3-23: HDMI Interface Block Diagram
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux