Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 80
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
• One of the GTH transceivers is wired to SFP/SFP+ Quad-Module connector (P2)
• One GTH transceiver is wired to the HDMI re-timer U94 and a set of GTH SMAs
Quad 128:
• MGTREFCLK0 - HDMI_SI5324_OUT_C_P/N
• MGTREFCLK1 - HDMI_RX_CLK_C_P/N
• Contains 3 GTH transceivers allocated to HDMI_TX/RX[0:2]_P/N
• Contains 1 GTH transceiver allocated to a set of SMA connectors (SMA_MGT_TX and RX
P/N)
Quad 129:
• MGTREFCLK0 - USER_MGT_SI570_CLOCK1_C_P/N
• MGTREFCLK1 - USER_SMA_MGT_CLOCK_C_P/N
• Contains 4 GTH transceivers allocated to FMC_HPC1_DP[4:7]_C2M/M2C_P/N
Quad 130:
• MGTREFCLK0 - FMC_HPC1_GBTCLK0_M2C_P/N
• MGTREFCLK1 - FMC_HPC1_GBTCLK1_M2C_P/N
• Contains 4 GTH transceivers allocated to FMC_HPC1_DP[0:3]_C2M/M2C_P/N
Quad 228:
• MGTREFCLK0 - FMC_HPC0_GBTCLK1_M2C_P/N
• MGTREFCLK1 - Not connected
• Contains 4 GTH transceivers allocated to FMC_HPC0_DP[4:7]_C2M/M2C_P/N
Quad 229:
• MGTREFCLK0 - FMC_HPC0_GBTCLK0_M2C_P/N
• MGTREFCLK1 - Not connected
• Contains 4 GTH transceivers allocated to FMC_HPC0_DP[0:3]_C2M/M2C_P/N
Quad 230:
• MGTREFCLK0 - USER_MGT_SI570_CLOCK2_C_P/N
• MGTREFCLK1 - SFP_SI5328_OUT_C_P/N
• Contains 4 GTH transceivers allocated to SFP[0:3]_TX/RX_P/N
GTH usage on the ZCU102 is shown in Figure 3-35.
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux