Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 82
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
SFP+
Four (4) PL-side GTH transceivers in Bank 228 are provided for the quad SFP+ interface.
Available GTH reference clocks include a programmable Si570 clock, and a jitter attenuated
recovered clock from a Si5328.
SFP+ modules typically provide an I2C based control interface. This I2C interface is
accessible for each individual SFP+ module through the I2C multiplexer topology on the
ZCU102.
HDMI
Three (3) PL-side GTH transceivers are dedicated for HDMI source and sink. Modes
supported are 4K, 2K at 60 f/s and 2160p60. External circuitry for interfacing TMDS signals
with the GTH transceivers is required.
SMA
One (1) MGT in Bank 128 is provided on a SMA connector pair. Available MGT clocks include
a user provided MGT reference clock on an SMA connector pair, and a programmable Si570
clock. Table 3-35 lists GTH bank 128 connections.
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux