Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 91
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
The ICM settings for lane functionality must be set consistent with the external U125
Pericom PI2DBS6212 GTR multiplexer settings to provide appropriate functionality on the
connectors wired to the PS-side GTR transceivers. The external GTR multiplexer selection is
controlled by the PS-side I2C0 GPIO port expander (U97) connected to the multiplexer’s "S"
input. S = 0 connects the A input to the B output, whereas S = 1, connects the A input to the
C output. The "S" select logic is implemented with GPIO pins to support the settings listed
in Table 3-43.
X-Ref Target - Figure 3-37
Figure 3-37: GTR External Switch Connectivity
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux