Xilinx ZCU111

ZCU111 Board User Guide 73
UG1271 (v1.1) August 6, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
SFP28
One PL-side GTY transceiver in bank 128 is provided for the quad SFP28 interface. Available
GTY reference clocks include a jitter attenuated recovered clock from a Si5382. SFP+
modules typically provide an I2C based control interface. This I2C interface is accessible for
each individual SFP28 module through the I2C multiplexer topology on the ZCU111 board.
The RFSoC U1 connections for each quad are referenced in Appendix B, Xilinx Design
Constraints.
For additional information on GTY transceivers, see the UltraScale Architecture GTY
Transceivers User Guide (UG578) [Ref 6].
PS-Side: GTR Transceivers
[Figure 2-1, callout 1]
The PS-side GTR transceiver bank 505 supports two DisplayPort transmit channels, USB (3.0)
and SATA, as shown in Figure 3-30.
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